e1000_fxhw.h

COPE the first practical network coding scheme which is developped on click

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 Copyright (c) 1999-2000, Intel Corporation 

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#ifndef _FXHW_
#include <linux/types.h>

#define _FXHW_

#define ASSERT(x) if(!(x)) panic("E1000: x")
#define DelayInMicroseconds(x) udelay(x)
#define DelayInMilliseconds(x) mdelay(x)

typedef uint8_t UCHAR, UINT8, BOOLEAN, *PUCHAR, *PUINT8;
typedef uint16_t USHORT, UINT16, *PUSHORT, *PUINT16;
typedef uint32_t UINT, ULONG, UINT32, *PUINT, *PULONG, *PUINT32;
typedef void VOID, *PVOID;
typedef uint64_t E1000_64_BIT_PHYSICAL_ADDRESS,
    *PE1000_64_BIT_PHYSICAL_ADDRESS;

#define IN
#define OUT
#define STATIC static

#define MSGOUT(S, A, B)     printk(S "\n", A, B)
#define DEBUGFUNC(F)        DEBUGOUT(F);

#define DEBUGOUT(S)
#define DEBUGOUT1(S, A)
#define DEBUGOUT2(S, A, B)

#define WritePciConfigWord(Reg, PValue) pci_write_config_word(Adapter->pci_dev, Reg, *PValue)

#define MAC_DECODE_SIZE (128 * 1024)

typedef enum _MAC_TYPE {
    MAC_WISEMAN_2_0 = 0,
    MAC_WISEMAN_2_1,
    MAC_LIVENGOOD,
    NUM_MACS
} MAC_TYPE, *PMAC_TYPE;

#define WISEMAN_2_0_REV_ID               2
#define WISEMAN_2_1_REV_ID               3

typedef enum _GIGABIT_MEDIA_TYPE {
    MEDIA_TYPE_COPPER = 0,
    MEDIA_TYPE_FIBER = 1,
    NUM_MEDIA_TYPES
} GIGABIT_MEDIA_TYPE, *PGIGABIT_MEDIA_TYPE;

typedef enum _SPEED_DUPLEX_TYPE {
    HALF_10 = 0,
    FULL_10 = 1,
    HALF_100 = 2,
    FULL_100 = 3
} SPEED_DUPLEX_TYPE, *PSPEED_DUPLEX_TYPE;

#define SPEED_10                        10
#define SPEED_100                      100
#define SPEED_1000                    1000
#define HALF_DUPLEX                      1
#define FULL_DUPLEX                      2

#define ENET_HEADER_SIZE                14
#define MAXIMUM_ETHERNET_PACKET_SIZE  1514
#define MINIMUM_ETHERNET_PACKET_SIZE    60
#define CRC_LENGTH                       4

#define MAX_JUMBO_FRAME_SIZE    (0x3F00)

#define ISL_CRC_LENGTH                         4

#define MAXIMUM_VLAN_ETHERNET_PACKET_SIZE   1514
#define MINIMUM_VLAN_ETHERNET_PACKET_SIZE     60
#define VLAN_TAG_SIZE                          4

#define ETHERNET_IEEE_VLAN_TYPE     0x8100
#define ETHERNET_IP_TYPE            0x0800
#define ETHERNET_IPX_TYPE           0x8037
#define ETHERNET_IPX_OLD_TYPE       0x8137
#define MAX_802_3_LEN_FIELD         0x05DC

#define ETHERNET_ARP_TYPE           0x0806
#define ETHERNET_XNS_TYPE           0x0600
#define ETHERNET_X25_TYPE           0x0805
#define ETHERNET_BANYAN_TYPE        0x0BAD
#define ETHERNET_DECNET_TYPE        0x6003
#define ETHERNET_APPLETALK_TYPE     0x809B
#define ETHERNET_SNA_TYPE           0x80D5
#define ETHERNET_SNMP_TYPE          0x814C

#define IP_OFF_MF_BIT               0x0002
#define IP_OFF_OFFSET_MASK          0xFFF8
#define IP_PROTOCOL_ICMP                 1
#define IP_PROTOCOL_IGMP                 2
#define IP_PROTOCOL_TCP                  6
#define IP_PROTOCOL_UDP               0x11
#define IP_PROTOCOL_IPRAW             0xFF

#define POLL_IMS_ENABLE_MASK (E1000_IMS_PCIE | E1000_IMS_RXDMT0 | E1000_IMS_RXSEQ)

#define IMS_ENABLE_MASK (E1000_IMS_RXT0 | E1000_IMS_TXDW | E1000_IMS_PCIE | E1000_IMS_RXDMT0 | E1000_IMS_RXSEQ | E1000_IMS_LSC | E1000_IMS_GPI_EN1)

#define E1000_RAR_ENTRIES 16

typedef struct _E1000_RECEIVE_DESCRIPTOR {
    E1000_64_BIT_PHYSICAL_ADDRESS BufferAddress;

    USHORT Length;
    USHORT Csum;
    UCHAR ReceiveStatus;
    UCHAR Errors;
    USHORT Special;

} E1000_RECEIVE_DESCRIPTOR, *PE1000_RECEIVE_DESCRIPTOR;

#define MIN_NUMBER_OF_DESCRIPTORS (8)
#define MAX_NUMBER_OF_DESCRIPTORS (0xFFF8)

#define E1000_RXD_STAT_DD        (0x01)
#define E1000_RXD_STAT_EOP       (0x02)

#define E1000_RXD_STAT_ISL       (0x04)
#define E1000_RXD_STAT_IXSM      (0x04)
#define E1000_RXD_STAT_VP        (0x08)
#define E1000_RXD_STAT_BPDU      (0x10)
#define E1000_RXD_STAT_TCPCS     (0x20)
#define E1000_RXD_STAT_IPCS      (0x40)

#define E1000_RXD_STAT_PIF       (0x80)

#define E1000_RXD_ERR_CE         (0x01)
#define E1000_RXD_ERR_SE         (0x02)
#define E1000_RXD_ERR_SEQ        (0x04)

#define E1000_RXD_ERR_ICE        (0x08)

#define E1000_RXD_ERR_CXE        (0x10)

#define E1000_RXD_ERR_TCPE       (0x20)
#define E1000_RXD_ERR_IPE        (0x40)

#define E1000_RXD_ERR_RXE        (0x80)

#define E1000_RXD_ERR_FRAME_ERR_MASK (E1000_RXD_ERR_CE | E1000_RXD_ERR_SE | E1000_RXD_ERR_SEQ | E1000_RXD_ERR_CXE | E1000_RXD_ERR_RXE)

#define E1000_RXD_SPC_VLAN_MASK  (0x0FFF)
#define E1000_RXD_SPC_PRI_MASK   (0xE000)
#define E1000_RXD_SPC_PRI_SHIFT  (0x000D)
#define E1000_RXD_SPC_CFI_MASK   (0x1000)
#define E1000_RXD_SPC_CFI_SHIFT  (0x000C)

#define E1000_TXD_DTYP_D        (0x00100000)
#define E1000_TXD_DTYP_C        (0x00000000)
#define E1000_TXD_POPTS_IXSM    (0x01)
#define E1000_TXD_POPTS_TXSM    (0x02)

typedef struct _E1000_TRANSMIT_DESCRIPTOR {
    E1000_64_BIT_PHYSICAL_ADDRESS BufferAddress;

    union {
        ULONG DwordData;
        struct _TXD_FLAGS {
            USHORT Length;
            UCHAR Cso;
            UCHAR Cmd;
        } Flags;
    } Lower;

    union {
        ULONG DwordData;
        struct _TXD_FIELDS {
            UCHAR TransmitStatus;
            UCHAR Css;
            USHORT Special;
        } Fields;
    } Upper;

} E1000_TRANSMIT_DESCRIPTOR, *PE1000_TRANSMIT_DESCRIPTOR;

typedef struct _E1000_TCPIP_CONTEXT_TRANSMIT_DESCRIPTOR {
    union {
        ULONG IpXsumConfig;
        struct _IP_XSUM_FIELDS {
            UCHAR Ipcss;
            UCHAR Ipcso;
            USHORT Ipcse;
        } IpFields;
    } LowerXsumSetup;

    union {
        ULONG TcpXsumConfig;
        struct _TCP_XSUM_FIELDS {
            UCHAR Tucss;
            UCHAR Tucso;
            USHORT Tucse;
        } TcpFields;
    } UpperXsumSetup;

    ULONG CmdAndLength;

    union {
        ULONG DwordData;
        struct _TCP_SEG_FIELDS {
            UCHAR Status;
            UCHAR HdrLen;
            USHORT Mss;
        } Fields;
    } TcpSegSetup;

} E1000_TCPIP_CONTEXT_TRANSMIT_DESCRIPTOR,
    *PE1000_TCPIP_CONTEXT_TRANSMIT_DESCRIPTOR;

typedef struct _E1000_TCPIP_DATA_TRANSMIT_DESCRIPTOR {
    E1000_64_BIT_PHYSICAL_ADDRESS BufferAddress;

    union {
        ULONG DwordData;
        struct _TXD_OD_FLAGS {
            USHORT Length;
            UCHAR TypLenExt;
            UCHAR Cmd;
        } Flags;
    } Lower;

    union {
        ULONG DwordData;
        struct _TXD_OD_FIELDS {
            UCHAR TransmitStatus;
            UCHAR Popts;
            USHORT Special;
        } Fields;
    } Upper;

} E1000_TCPIP_DATA_TRANSMIT_DESCRIPTOR,
    *PE1000_TCPIP_DATA_TRANSMIT_DESCRIPTOR;

#define E1000_TXD_CMD_EOP   (0x01000000)
#define E1000_TXD_CMD_IFCS  (0x02000000)

#define E1000_TXD_CMD_IC    (0x04000000)

#define E1000_TXD_CMD_RS    (0x08000000)
#define E1000_TXD_CMD_RPS   (0x10000000)

#define E1000_TXD_CMD_DEXT  (0x20000000)
#define E1000_TXD_CMD_ISLVE (0x40000000)

#define E1000_TXD_CMD_IDE   (0x80000000)

#define E1000_TXD_STAT_DD   (0x00000001)
#define E1000_TXD_STAT_EC   (0x00000002)
#define E1000_TXD_STAT_LC   (0x00000004)
#define E1000_TXD_STAT_TU   (0x00000008)

#define E1000_TXD_CMD_TCP   (0x01000000)
#define E1000_TXD_CMD_IP    (0x02000000)
#define E1000_TXD_CMD_TSE   (0x04000000)

#define E1000_TXD_STAT_TC   (0x00000004)

#define E1000_NUM_UNICAST          (16)
#define E1000_MC_TBL_SIZE          (128)

#define E1000_VLAN_FILTER_TBL_SIZE (128)

enum {
    FLOW_CONTROL_NONE = 0,
    FLOW_CONTROL_RECEIVE_PAUSE = 1,
    FLOW_CONTROL_TRANSMIT_PAUSE = 2,
    FLOW_CONTROL_FULL = 3,
    FLOW_CONTROL_HW_DEFAULT = 0xFF
};

typedef struct {
    volatile unsigned int Low;
    volatile unsigned int High;
} RECEIVE_ADDRESS_REGISTER_PAIR;

typedef struct _E1000_REGISTERS {

    volatile unsigned int Ctrl;
    volatile unsigned int Pad1;
    volatile unsigned int Status;
    volatile unsigned int Pad2;
    volatile unsigned int Eecd;
    volatile unsigned int Pad3;
    volatile unsigned int Exct;
    volatile unsigned int Pad4;
    volatile unsigned int Mdic;
    volatile unsigned int Pad5;
    volatile unsigned int Fcal;
    volatile unsigned int Fcah;
    volatile unsigned int Fct;
    volatile unsigned int Pad6;

    volatile unsigned int Vet;
    volatile unsigned int Pad7;

    RECEIVE_ADDRESS_REGISTER_PAIR Rar[16];

    volatile unsigned int Icr;
    volatile unsigned int Pad8;
    volatile unsigned int Ics;
    volatile unsigned int Pad9;
    volatile unsigned int Ims;
    volatile unsigned int Pad10;
    volatile unsigned int Imc;
    volatile unsigned char Pad11[0x24];

    volatile unsigned int Rctl;
    volatile unsigned int Pad12;
    volatile unsigned int PadRdtr0;
    volatile unsigned int Pad13;
    volatile unsigned int PadRdbal0;
    volatile unsigned int PadRdbah0;
    volatile unsigned int PadRdlen0;
    volatile unsigned int Pad14;
    volatile unsigned int PadRdh0;
    volatile unsigned int Pad15;
    volatile unsigned int PadRdt0;
    volatile unsigned int Pad16;
    volatile unsigned int Rdtr1;
    volatile unsigned int Pad17;
    volatile unsigned int Rdbal1;
    volatile unsigned int Rdbah1;
    volatile unsigned int Rdlen1;
    volatile unsigned int Pad18;
    volatile unsigned int Rdh1;
    volatile unsigned int Pad19;
    volatile unsigned int Rdt1;
    volatile unsigned char Pad20[0x0C];
    volatile unsigned int PadFcrth;
    volatile unsigned int Pad21;
    volatile unsigned int PadFcrtl;
    volatile unsigned int Pad22;
    volatile unsigned int Fcttv;
    volatile unsigned int Pad23;
    volatile unsigned int Txcw;
    volatile unsigned int Pad24;
    volatile unsigned int Rxcw;
    volatile unsigned char Pad25[0x7C];
    volatile unsigned int Mta[(128)];

    volatile unsigned int Tctl;
    volatile unsigned int Pad26;
    volatile unsigned int Tqsal;
    volatile unsigned int Tqsah;
    volatile unsigned int Tipg;
    volatile unsigned int Pad27;
    volatile unsigned int Tqc;
    volatile unsigned int Pad28;