📄 e1000_main.c
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/***************************************************************************** Name: e1000_print_brd_conf** Description: This routine printd the board configuration.** Author: IntelCorporation** Born on Date: 7/24/97** Arguments: * bdp - Ptr to this card's DL_bdconfig structure** Returns:* NONE** Modification log:* Date Who Description* -------- --- -------------------------------------------------------- *****************************************************************************/static voide1000_print_brd_conf(bd_config_t * bdp){ PADAPTER_STRUCT Adapter = (PADAPTER_STRUCT) bdp->bddp; if(Adapter->LinkIsActive == TRUE) printk("%s: Mem:0x%p IRQ:%d Speed:%ld Mbps Dx:%s FlowCtl:%02x\n\n", bdp->device->name, (void *) bdp->mem_start, bdp->irq_level, Adapter->cur_line_speed, Adapter->FullDuplex == FULL_DUPLEX ? "Full" : "Half", Adapter->FlowControl); else printk("%s: Mem:0x%p IRQ:%d Speed:N/A Dx:N/A\n\n", bdp->device->name, (void *) bdp->mem_start, bdp->irq_level);}/****************************************************************************** Name: SetupTransmitStructures** Description: This routine initializes all of the transmit related* structures. This includes the Transmit descriptors * and the TX_SW_PACKETs structures.** NOTE -- The device must have been reset before this routine* is called.** Author: IntelCorporation** Born on Date: 6/14/97** Arguments:* Adapter - A pointer to our context sensitive "Adapter" structure.* DebugPrint - print debug or not. ( not used in this driver )*** Returns:* (none)** Modification log:* Date Who Description* -------- --- --------------------------------------------------------******************************************************************************/static voidSetupTransmitStructures(PADAPTER_STRUCT Adapter, boolean_t DebugPrint){ UINT i; if (e1000_debug_level >= 1) printk("SetupTransmitStructures\n"); /********************************************************************** * Setup TxSwPackets **********************************************************************/ /* * The transmit algorithm parameters like the append size * and copy size which are used for the transmit algorithm and * are configurable. */ Adapter->TxIntDelay = e1000_txint_delay; /************************************************** * Setup TX Descriptors ***************************************************/ /* Initialize all of the Tx descriptors to zeros */ memset((PVOID) Adapter->FirstTxDescriptor, 0, (sizeof(E1000_TRANSMIT_DESCRIPTOR)) * Adapter->NumTxDescriptors); /* Setup TX descriptor pointers */ Adapter->NextAvailTxDescriptor = Adapter->FirstTxDescriptor; Adapter->OldestUsedTxDescriptor = Adapter->FirstTxDescriptor; /* Setup the Transmit Control Register (TCTL). */ if (Adapter->FullDuplex) { E1000_WRITE_REG(Tctl, (E1000_TCTL_PSP | E1000_TCTL_EN | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | (E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT))); } else { E1000_WRITE_REG(Tctl, (E1000_TCTL_PSP | E1000_TCTL_EN | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT))); } /*********************************************************** * Setup Hardware TX Registers ************************************************************/ /* Setup HW Base and Length of Tx descriptor area */ E1000_WRITE_REG(Tdbal, virt_to_bus((void *) Adapter->FirstTxDescriptor)); E1000_WRITE_REG(Tdbah, 0); E1000_WRITE_REG(Tdl, (Adapter->NumTxDescriptors * sizeof(E1000_TRANSMIT_DESCRIPTOR))); /* Setup our HW Tx Head & Tail descriptor pointers */ E1000_WRITE_REG(Tdh, 0); E1000_WRITE_REG(Tdt, 0); /* Zero out the Tx Queue State registers -- we don't use this mechanism. */ if (Adapter->MacType < MAC_LIVENGOOD) { E1000_WRITE_REG(Tqsal, 0); E1000_WRITE_REG(Tqsah, 0); } /* Set the Transmit IPG register with default values. * Three values are used to determine when we transmit a packet on the * wire: IPGT, IPGR1, & IPGR2. IPGR1 & IPGR2 have no meaning in full * duplex. Due to the state machine implimentation all values are * effectivly 2 higher i.e. a setting of 10 causes the hardware to * behave is if it were set to 1 * 2. These settigs are in "byte times". For example, an IPGT setting * of 10 plus the state machine delay of 2 is 12 byte time = 96 bit * times. */ /* Set the Transmit IPG register with default values. */ switch (Adapter->MacType) { case MAC_LIVENGOOD: if(Adapter->MediaType == MEDIA_TYPE_FIBER) { E1000_WRITE_REG(Tipg, DEFAULT_LVGD_TIPG_IPGT_FIBER | (DEFAULT_LVGD_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT) | (DEFAULT_LVGD_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT)); } else { E1000_WRITE_REG(Tipg, DEFAULT_LVGD_TIPG_IPGT_COPPER | (DEFAULT_LVGD_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT) | (DEFAULT_LVGD_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT)); } break; case MAC_WISEMAN_2_0: case MAC_WISEMAN_2_1: default: E1000_WRITE_REG(Tipg, DEFAULT_WSMN_TIPG_IPGT | (DEFAULT_WSMN_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT) | (DEFAULT_WSMN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT)); break; } /* * Set the Transmit Interrupt Delay register with the vaule for the * transmit interrupt delay */ E1000_WRITE_REG(Tidv, Adapter->TxIntDelay);}/****************************************************************************** Name: SetupReceiveStructures** Description: This routine initializes all of the receive related* structures. This includes the receive descriptors, the* actual receive buffers, and the RX_SW_PACKET software structures.** NOTE -- The device must have been reset before this routine* is called.** Author: IntelCorporation** Born on Date: 6/27/97** Arguments:* Adapter - A pointer to our context sensitive "Adapter" structure.** DebugPrint - A variable that indicates whether a "debug" version of* the driver should print debug strings to the terminal.** flag - indicates if the driver should indicate link* Returns:* (none)** Modification log:* Date Who Description* -------- --- --------------------------------------------------------******************************************************************************/static intSetupReceiveStructures(bd_config_t *bdp, boolean_t DebugPrint, boolean_t flag){ PE1000_RECEIVE_DESCRIPTOR RxDescriptorPtr; UINT i; PADAPTER_STRUCT Adapter = bdp->bddp; uint32_t RegRctl = 0; if (e1000_debug_level >= 1) printk("SetupReceiveStructures\n"); /* * Set the value of the maximum number of packets that will be processed * in the interrupt context from the file space.c */ Adapter->MaxNumReceivePackets = RxDescriptors[Adapter->bd_number];; /* * Set the Receive interrupt delay and also the maximum number of times * the transmit and receive interrupt are going to be processed from the * space.c file */ Adapter->RxIntDelay = e1000_rxint_delay; Adapter->MaxDpcCount = e1000_maxdpc_count; /* Initialize all of the Rx descriptors to zeros */ memset((PVOID) Adapter->FirstRxDescriptor, 0, (sizeof(E1000_RECEIVE_DESCRIPTOR)) * Adapter->NumRxDescriptors); for (i = 0, RxDescriptorPtr = Adapter->FirstRxDescriptor; i < Adapter->NumRxDescriptors; i++, RxDescriptorPtr++) { if (Adapter->RxSkBuffs[i] == NULL) printk ("SetupReceiveStructures rcv buffer memory not allocated"); else { PVOID va = Adapter->RxSkBuffs[i]->tail; RxDescriptorPtr->BufferAddress = 0; RxDescriptorPtr->BufferAddress += virt_to_bus(va); } } /* Setup our descriptor pointers */ Adapter->NextRxDescriptorToCheck = Adapter->FirstRxDescriptor; Adapter->NextRxIndexToFill = 0; /* * Set up all the RCTL fields */ E1000_WRITE_REG(Rctl, 0); E1000_WRITE_REG(Rdtr0, (Adapter->RxIntDelay | E1000_RDT0_FPDB)); /* Setup HW Base and Length of Rx descriptor area */ E1000_WRITE_REG(Rdbal0, virt_to_bus((void *) Adapter->FirstRxDescriptor)); E1000_WRITE_REG(Rdbah0, 0); E1000_WRITE_REG(Rdlen0, (Adapter->NumRxDescriptors * sizeof(E1000_RECEIVE_DESCRIPTOR))); /* Setup our HW Rx Head & Tail descriptor pointers */ E1000_WRITE_REG(Rdh0, 0); E1000_WRITE_REG(Rdt0, (((unsigned long) Adapter->LastRxDescriptor - (unsigned long) Adapter->FirstRxDescriptor) >> 4)); /* Zero out the registers associated with the second receive descriptor * ring, because we don't use that ring. */ if (Adapter->MacType < MAC_LIVENGOOD) { E1000_WRITE_REG(Rdbal1, 0); E1000_WRITE_REG(Rdbah1, 0); E1000_WRITE_REG(Rdlen1, 0); E1000_WRITE_REG(Rdh1, 0); E1000_WRITE_REG(Rdt1, 0); } /* Setup the Receive Control Register (RCTL), and ENABLE the receiver. * The initial configuration is to: Enable the receiver, accept * broadcasts, discard bad packets (and long packets), disable VLAN filter * checking, set the receive descriptor minimum threshold size to 1/2, * and the receive buffer size to 2k. */ RegRctl = E1000_RCTL_EN | /* Enable Receive Unit */ E1000_RCTL_BAM | /* Accept Broadcast Packets */ (Adapter->MulticastFilterType << E1000_RCTL_MO_SHIFT) | E1000_RCTL_RDMTS0_HALF | E1000_RCTL_LBM_NO; /* Loopback Mode = none */ switch (Adapter->RxBufferLen) { case E1000_RXBUFFER_2048: default: RegRctl |= E1000_RCTL_SZ_2048; break; case E1000_RXBUFFER_4096: RegRctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; break; case E1000_RXBUFFER_8192: RegRctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; break; case E1000_RXBUFFER_16384: RegRctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; break; } if(SBP[Adapter->bd_number] > 0) { RegRctl |= E1000_RCTL_SBP; } E1000_WRITE_REG(Rctl, RegRctl); /* * Check and report the status of the link */ if (!(E1000_READ_REG(Status) & E1000_STATUS_LU) && (flag == TRUE)) printk("e1000: %s Link is Down\n", bdp->device->name); Adapter->DoRxResetFlag = B_FALSE; return (0);}/****************************************************************************** Name: UpdateStatsCounters** Description: This routine will dump and reset the E10001000's internal* Statistics counters. The current stats dump values will be* added to the "Adapter's" overall statistics.** Author: IntelCorporation** Born on Date: 6/13/97** Arguments:* Adapter - A pointer to our context sensitive "Adapter" structure.** Returns:* (none)** Modification log:* Date Who Description* -------- --- --------------------------------------------------------******************************************************************************/static VOIDUpdateStatsCounters(bd_config_t * bdp){ PADAPTER_STRUCT Adapter; net_device_stats_t *stats; Adapter = bdp->bddp; stats = &bdp->net_stats; /* Add the values from the chip's statistics registers to the total values * that we keep in software. These registers clear on read. */ Adapter->RcvCrcErrors += E1000_READ_REG(Crcerrs); Adapter->RcvSymbolErrors += E1000_READ_REG(Symerrs); Adapter->RcvMissedPacketsErrors += E1000_READ_REG(Mpc); Adapter->DeferCount += E1000_READ_REG(Dc); Adapter->RcvSequenceErrors += E1000_READ_REG(Sec); Adapter->RcvLengthErrors += E1000_READ_REG(Rlec); Adapter->RcvXonFrame += E1000_READ_REG(Xonrxc); Adapter->TxXonFrame += E1000_READ_REG(Xontxc); Adapter->RcvXoffFrame += E1000_READ_REG(Xoffrxc); Adapter->TxXoffFrame += E1000_READ_REG(Xofftxc); Adapter->Rcv64 += E1000_READ_REG(Prc64); Adapter->Rcv65 += E1000_READ_REG(Prc127); Adapter->Rcv128 += E1000_READ_REG(Prc255); Adapter->Rcv256 += E1000_READ_REG(Prc511); Adapter->Rcv512 += E1000_READ_REG(Prc1023); Adapter->Rcv1024 += E1000_READ_REG(Prc1522); Adapter->GoodReceives += E1000_READ_REG(Gprc); Adapter->RcvBroadcastPkts += E1000_READ_REG(Bprc); Adapter->RcvMulticastPkts += E1000_READ_REG(Mprc); Adapter->GoodTransmits += E1000_READ_REG(Gptc); Adapter->Rnbc += E1000_READ_REG(Rnbc); Adapter->RcvUndersizeCnt += E1000_READ_REG(Ruc); Adapter->RcvFragment += E1000_READ_REG(Rfc); Adapter->RcvOversizeCnt += E1000_READ_REG(Roc); Adapter->RcvJabberCnt += E1000_READ_REG(Rjc); Adapter->TotPktRcv += E1000_READ_REG(Tpr); Adapter->TotPktTransmit += E1000_READ_REG(Tpt); Adapter->TrsPkt64 += E1000_READ_REG(Ptc64); Adapter->TrsPkt65 += E1000_READ_REG(Ptc127); Adapter->TrsPkt128 += E1000_READ_REG(Ptc255); Adapter->TrsPkt256 += E1000_READ_REG(Ptc511); Adapter->TrsPkt512 += E1000_READ_REG(Ptc1023); Adapter->TrsPkt1024 += E1000_READ_REG(Ptc1522); Adapter->TrsMulticastPkt += E1000_READ_REG(Mptc); Adapter->TrsBroadcastPkt += E1000_READ_REG(Bptc); Adapter->TxAbortExcessCollisions += E1000_READ_REG(Ecol); Adapter->TxLateCollisions += E1000_READ_REG(Latecol); Adapter->TotalCollisions += E1000_READ_REG(Colc); Adapter->SingleCollisions += E1000_READ_REG(Scc); Adapter->MultiCollisions += E1000_READ_REG(Mcc); Adapter->FCUnsupported += E1000_READ_REG(Fcruc); /* The byte count registers are 64-bits, to reduce the chance of overflow * The entire 64-bit
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