e1000.h

COPE the first practical network coding scheme which is developped on click

*   e1000_pci.h                                                          *
* Abstract:                                                              *
*   This header file contains PCI related constants and bit definitions. *
*                                                                        *
*   This driver runs on the following hardware:                          *
*   - E10001000 based PCI gigabit ethernet adapters (aka Kodiak)         *
*                                                                        *
* Environment:                                                           *
*   Kernel Mode -                                                        *
*                                                                        *
* Source History:                                                        *
*   The contents of this file is based somewhat on code developed for    *
*   Intel Pro/100 family (Speedo1 and Speedo3).                          *
*                                                                        *
*   March 7, 1997                                                        *
*   1st created - Ported from E100B pci.h file                           *
*                                                                        *
*************************************************************************/

/* typedefs for each NOS */
#if defined LINUX

/* PCI Device ID - for internal use */
#define PCI_DEV_NO              0x00FF
#define PCI_BUS_NO              0xFF00

/* max number of pci buses */
#define MAX_PCI_BUSES   0xFF

/* number of PCI config bytes to access */
#define PCI_BYTE   1
#define PCI_WORD   2
#define PCI_DWORD   4

/* PCI access methods */
#define P_CONF_T1   1
#define P_CONF_T2   2
#define P_TEST_PATN     0xCDEF

#define PO_DEV_NO       11
#define PO_BUS_NO       16
#define P_CSPACE   0x80000000
#endif


/*----------------------------------------------------------------------*/

#ifndef _PCI_H
#define _PCI_H


/* Maximum number of PCI devices */
#define PCI_MAX_DEVICES         32

/*-------------------------------------------------------------------------*/
/* PCI configuration hardware ports                                        */
/*-------------------------------------------------------------------------*/
#define CF1_CONFIG_ADDR_REGISTER    0x0CF8
#define CF1_CONFIG_DATA_REGISTER    0x0CFC
#define CF2_SPACE_ENABLE_REGISTER   0x0CF8
#define CF2_FORWARD_REGISTER        0x0CFA
#define CF2_BASE_ADDRESS            0xC000


/*-------------------------------------------------------------------------*/
/* Configuration Space Header                                              */
/*-------------------------------------------------------------------------*/
typedef struct _PCI_CONFIG_STRUC {
    USHORT PciVendorId;            /* PCI Vendor ID */
    USHORT PciDeviceId;            /* PCI Device ID */
    USHORT PciCommand;
    USHORT PciStatus;
    UCHAR PciRevisionId;
    UCHAR PciClassCode[3];
    UCHAR PciCacheLineSize;
    UCHAR PciLatencyTimer;
    UCHAR PciHeaderType;
    UCHAR PciBIST;
    ULONG PciBaseReg0;
    ULONG PciBaseReg1;
    ULONG PciBaseReg2;
    ULONG PciBaseReg3;
    ULONG PciBaseReg4;
    ULONG PciBaseReg5;
    ULONG PciCardbusCISPtr;
    USHORT PciSubSysVendorId;
    USHORT PciSubSysDeviceId;
    ULONG PciExpROMAddress;
    ULONG PciReserved2;
    ULONG PciReserved3;
    UCHAR PciInterruptLine;
    UCHAR PciInterruptPin;
    UCHAR PciMinGnt;
    UCHAR PciMaxLat;
} PCI_CONFIG_STRUC, *PPCI_CONFIG_STRUC;

/*-------------------------------------------------------------------------*/
/* PCI Configuration Space Register Offsets                                */
/* Refer To The PCI Specification For Detailed Explanations                */
/*-------------------------------------------------------------------------*/
#define PCI_VENDOR_ID_REGISTER      0x00    /* PCI Vendor ID Register */
#define PCI_DEVICE_ID_REGISTER      0x02    /* PCI Device ID Register */
#define PCI_CONFIG_ID_REGISTER      0x00    /* PCI Configuration ID Register */
#define PCI_COMMAND_REGISTER        0x04    /* PCI Command Register */
#define PCI_STATUS_REGISTER         0x06    /* PCI Status Register */
#define PCI_REV_ID_REGISTER         0x08    /* PCI Revision ID Register */
#define PCI_CLASS_CODE_REGISTER     0x09    /* PCI Class Code Register */
#define PCI_CACHE_LINE_REGISTER     0x0C    /* PCI Cache Line Register */

#define PCI_BIST_REGISTER           0x0F    /* PCI Built-In SelfTest Register */
#define PCI_BAR_0_REGISTER          0x10    /* PCI Base Address Register 0 */
#define PCI_BAR_1_REGISTER          0x14    /* PCI Base Address Register 1 */
#define PCI_BAR_2_REGISTER          0x18    /* PCI Base Address Register 2 */
#define PCI_BAR_3_REGISTER          0x1C    /* PCI Base Address Register 3 */
#define PCI_BAR_4_REGISTER          0x20    /* PCI Base Address Register 4 */
#define PCI_BAR_5_REGISTER          0x24    /* PCI Base Address Register 5 */
#define PCI_SUBVENDOR_ID_REGISTER   0x2C    /* PCI SubVendor ID Register */
#define PCI_SUBDEVICE_ID_REGISTER   0x2E    /* PCI SubDevice ID Register */
#define PCI_EXPANSION_ROM           0x30    /* PCI Expansion ROM Base Register */
#define PCI_MIN_GNT_REGISTER        0x3E    /* PCI Min-Gnt Register */
#define PCI_MAX_LAT_REGISTER        0x3F    /* PCI Max_Lat Register */
#define PCI_TRDY_TIMEOUT_REGISTER   0x40    /* PCI TRDY Timeout Register */
#define PCI_RETRY_TIMEOUT_REGISTER  0x41    /* PCI Retry Timeout Register */



/*-------------------------------------------------------------------------*/
/* PCI Class Code Definitions                                              */
/* Configuration Space Header                                              */
/*-------------------------------------------------------------------------*/
#define PCI_BASE_CLASS      0x02    /* Base Class - Network Controller */
#define PCI_SUB_CLASS       0x00    /* Sub Class - Ethernet Controller */
#define PCI_PROG_INTERFACE  0x00    /* Prog I/F - Ethernet COntroller */

/*-------------------------------------------------------------------------*/
/* PCI Command Register Bit Definitions */
/* Configuration Space Header */
/*-------------------------------------------------------------------------*/
#define CMD_IO_SPACE                0x0001    /* BIT_0 */
#define CMD_MEMORY_SPACE            0x0002    /* BIT_1 */
#define CMD_BUS_MASTER              0x0004    /* BIT_2 */
#define CMD_SPECIAL_CYCLES          0x0008    /* BIT_3 */
#define CMD_MEM_WRT_INVALIDATE      0x0010    /* BIT_4 */
#define CMD_VGA_PALLETTE_SNOOP      0x0020    /* BIT_5 */
#define CMD_PARITY_RESPONSE         0x0040    /* BIT_6 */
#define CMD_WAIT_CYCLE_CONTROL      0x0080    /* BIT_7 */
#define CMD_SERR_ENABLE             0x0100    /* BIT_8 */
#define CMD_BACK_TO_BACK            0x0200    /* BIT_9 */

/*-------------------------------------------------------------------------*/
/* PCI Status Register Bit Definitions                                     */
/* Configuration Space Header                                              */
/*-------------------------------------------------------------------------*/
#define STAT_BACK_TO_BACK           0x0080    /* BIT_7 */
#define STAT_DATA_PARITY            0x0100    /* BIT_8 */
#define STAT_DEVSEL_TIMING          0x0600    /* BIT_9_10 */
#define STAT_SIGNAL_TARGET_ABORT    0x0800    /* BIT_11 */
#define STAT_RCV_TARGET_ABORT       0x1000    /* BIT_12 */
#define STAT_RCV_MASTER_ABORT       0x2000    /* BIT_13 */
#define STAT_SIGNAL_MASTER_ABORT    0x4000    /* BIT_14 */
#define STAT_DETECT_PARITY_ERROR    0x8000    /* BIT_15 */

/*-------------------------------------------------------------------------*/
/* PCI Base Address Register For Memory (BARM) Bit Definitions */
/* Configuration Space Header */
/*-------------------------------------------------------------------------*/
#define BARM_LOCATE_BELOW_1_MEG     0x0002    /* BIT_1 */
#define BARM_LOCATE_IN_64_SPACE     0x0004    /* BIT_2 */
#define BARM_PREFETCHABLE           0x0008    /* BIT_3 */

/*-------------------------------------------------------------------------*/
/* PCI Base Address Register For I/O (BARIO) Bit Definitions               */
/* Configuration Space Header                                              */
/*-------------------------------------------------------------------------*/
#define BARIO_SPACE_INDICATOR       0x0001    /* BIT_0 */

/*-------------------------------------------------------------------------*/
/* PCI BIOS Definitions                                                    */
/* Refer To The PCI BIOS Specification                                     */
/*-------------------------------------------------------------------------*/
/*- Function Code List */
#define PCI_FUNCTION_ID         0xB1    /* AH Register */
#define PCI_BIOS_PRESENT        0x01    /* AL Register */
#define FIND_PCI_DEVICE         0x02    /* AL Register */
#define FIND_PCI_CLASS_CODE     0x03    /* AL Register */
#define GENERATE_SPECIAL_CYCLE  0x06    /* AL Register */
#define READ_CONFIG_BYTE        0x08    /* AL Register */
#define READ_CONFIG_WORD        0x09    /* AL Register */
#define READ_CONFIG_DWORD       0x0A    /* AL Register */
#define WRITE_CONFIG_BYTE       0x0B    /* AL Register */
#define WRITE_CONFIG_WORD       0x0C    /* AL Register */
#define WRITE_CONFIG_DWORD      0x0D    /* AL Register */

/*- Function Return Code List */
#define SUCCESSFUL              0x00
#define FUNC_NOT_SUPPORTED      0x81
#define BAD_VENDOR_ID           0x83
#define DEVICE_NOT_FOUND        0x86
#define BAD_REGISTER_NUMBER     0x87

/*- PCI BIOS Calls */
#define PCI_BIOS_INTERRUPT      0x1A    /* PCI BIOS Int 1Ah Function Call */
#define PCI_PRESENT_CODE        0x20494350    /* Hex Equivalent Of 'PCI ' */

#define PCI_SERVICE_IDENTIFIER  0x49435024    /* ASCII Codes for 'ICP$' */

/*-------------------------------------------------------------------------*/
/* Device and Vendor IDs                                                   */
/*-------------------------------------------------------------------------*/
#define E1000_DEVICE_ID        0x1000
#define WISEMAN_DEVICE_ID      0x1000
#define LIVENGOOD_FIBER_DEVICE_ID    0x1001
#define LIVENGOOD_COPPER_DEVICE_ID   0x1004
#define E1000_VENDOR_ID        0x8086

#define SPLASH_DEVICE_ID        0x1226
#define SPLASH_VENDOR_ID        0x8086
#define SPEEDO_DEVICE_ID        0x1227
#define SPEEDO_VENDOR_ID        0x8086
#define D100_DEVICE_ID          0x1229
#define D100_VENDOR_ID          0x8086
#define NITRO3_DEVICE_ID        0x5201
#define NITRO3_VENDOR_ID        0x8086
#define XXPS_BRIDGE_DEVICE_ID   0x1225
#define XXPS_BRIDGE_VENDOR_ID   0x8086
#define OPB0_BRIDGE_DEVICE_ID   0x84C4
#define OPB0_BRIDGE_VENDOR_ID   0x8086


#endif                            /* PCI_H */




/*
 * e1000_externs.h
 * 
 *  This file has all the defines for the functions in various header files
 */
#ifdef E1000_MAIN_STATIC
static void e1000_print_brd_conf(bd_config_t *);
static int e1000_init(bd_config_t *);
static int e1000_runtime_init(bd_config_t *);

static boolean_t e1000_sw_init(bd_config_t *);
static void *malloc_contig(int);
static void free_contig(void *);
static void e1000_dealloc_space(bd_config_t *);
static bd_config_t *e1000_alloc_space(void);

static boolean_t e1000_find_pci_device(pci_dev_t *, PADAPTER_STRUCT);

static void e1000_watchdog(device_t *);
static void e1000_intr(int, void *, struct pt_regs *);

static void SetupTransmitStructures(PADAPTER_STRUCT, boolean_t);
static int SetupReceiveStructures(bd_config_t *, boolean_t, boolean_t);
static int ReadNodeAddress(PADAPTER_STRUCT, PUCHAR);
static int e1000_set_promisc(bd_config_t *, int flag);
static void e1000DisableInterrupt(PADAPTER_STRUCT);
static void e1000EnableInterrupt(PADAPTER_STRUCT);
static void e1000DisableInterrupt(PADAPTER_STRUCT);
static struct sk_buff* ProcessTransmitInterrupts(bd_config_t *, int);
static void ProcessReceiveInterrupts(bd_config_t *);
static void UpdateStatsCounters(bd_config_t *);
static uint_t SendBuffer(struct sk_buff *, bd_config_t *, int, int);

int e1000_probe(void);
static int e1000_open(device_t *);
static int e1000_close(device_t *);
static int e1000_xmit_frame(struct sk_buff *, device_t *);
static struct net_device_stats *e1000_get_stats(device_t *);
static int e1000_change_mtu(device_t *, int);
static int e1000_set_mac(device_t *, void *);
static void e1000_set_multi(device_t *);
static void e1000_check_options(int board);
static boolean_t DetectKnownChipset(PADAPTER_STRUCT);
static int e1000_GetBrandingMesg(uint16_t dev, uint16_t sub_ven, uint16_t sub_dev);
#endif
extern void AdapterStop(PADAPTER_STRUCT);
extern ushort_t ReadEepromWord(PADAPTER_STRUCT, ushort_t);
extern boolean_t ValidateEepromChecksum(PADAPTER_STRUCT);
extern void CheckForLink(PADAPTER_STRUCT);
extern BOOLEAN InitializeHardware(PADAPTER_STRUCT Adapter);
extern BOOLEAN SetupFlowControlAndLink(PADAPTER_STRUCT Adapter);
extern VOID GetSpeedAndDuplex(PADAPTER_STRUCT Adapter, PUINT16 Speed, PUINT16 Duplex);
extern VOID ConfigFlowControlAfterLinkUp(PADAPTER_STRUCT Adapter);
extern VOID ClearHwStatsCounters(PADAPTER_STRUCT Adapter);

/*************************************************************************
*                                                                        *
* Module Name:                                                           *
*   pci.h                                                                *
* Abstract:                                                              *
*   This header file contains PCI related constants and bit definitions. *
*                                                                        *
*   This driver runs on the following hardware:                          *
*   - E10001000 based PCI gigabit ethernet adapters (aka Kodiak)         *
*                                                                        *
* Environment:                                                           *
*   Kernel Mode -                                                        *
*                                                                        *
* Source History:                                                        *
*   The contents of this file is based somewhat on code developed for    *
*   Intel Pro/100 family (Speedo1 and Speedo3).                          *
*                                                                        *
*   March 7, 1997                                                        *
*   1st created - Ported from E100B pci.h file                           *
*                                                                        *
*************************************************************************/
#ifndef _E1K_PCI_H
#define _E1K_PCI_H

/*-------------------------------------------------------------------------*/
/* Device and Vendor IDs                                                   */
/*-------------------------------------------------------------------------*/
#define E1000_DEVICE_ID        0x1000
#define E1000_VENDOR_ID        0x8086

#define SPLASH_DEVICE_ID        0x1226
#define SPLASH_VENDOR_ID        0x8086
#define SPEEDO_DEVICE_ID        0x1227
#define SPEEDO_VENDOR_ID        0x8086
#define D100_DEVICE_ID          0x1229
#define D100_VENDOR_ID          0x8086
#define NITRO3_DEVICE_ID        0x5201
#define NITRO3_VENDOR_ID        0x8086
#define XXPS_BRIDGE_DEVICE_ID   0x1225
#define XXPS_BRIDGE_VENDOR_ID   0x8086
#define OPB0_BRIDGE_DEVICE_ID   0x84C4
#define OPB0_BRIDGE_VENDOR_ID   0x8086

#define INTEL_440BX_AGP         0x7192
#define INTEL_440BX             0x7190
#define INTEL_440GX             0x71A0
#define INTEL_440LX_EX          0x7180
#define INTEL_440FX             0x1237
#define INTEL_430TX             0x7100
#define INTEL_450NX_PXB         0x84CB
#define INTEL_450KX_GX_PB       0x84C4


/**********************************************************************
** Other component's device number in PCI config space
**********************************************************************/

#define PXB_0A_DEVNO            0x12
#define PXB_0B_DEVNO            0x13
#define PXB_1A_DEVNO            0x14
#define PXB_1B_DEVNO            0x15

#define PB0_DEVNO               0x19
#define PB1_DEVNO               0x1A

#define PXB_C0_REV_ID           0x4


#endif                            /* PCI_H */
#endif                            /* _E1000_H_ */