📄 mt6188a1_drv.c
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{ CW( 6, 1), 0x0F, 0x10 }, //CW6_1 [7:4] 1 //TAR[3:0]
{ CW( 7, 1), 0xFC, 0x00 }, //CW7_1 [1:0] 0 //CAL[1:0]
{ CW( 13, 0), 0x00, 0x88 }, //CW13_0 [7:0] 136 //pilot
{ CW( 97, 1), 0xE0, 0x10 }, //CW97_1 [4:0] 16 //FRTUNE1[4:0]
{ CW( 97, 0), 0xE0, 0x00 }, //CW97_0 [4:0] 0 //FRTUNE2[4:0]
{ CW( 98, 1), 0x00, 0x80 }, //CW98_1 [7:0] 128 //DMTUNE1I[7:0]
{ CW( 98, 0), 0x00, 0x00 }, //CW98_0 [7:0] 0 //DMTUNE2I[3:0]
{ CW( 99, 1), 0x00, 0x80 }, //CW99_1 [7:0] 128 //DMTUNE1Q[7:0]
{ CW( 99, 0), 0xF0, 0x00 }, //CW99_0 [3:0] 0 //DMTUNE2Q[3:0]
{ CW(101, 0), 0xF8, 0x04 }, //CW101_0 [2:0] 4 //LPF[2:0]
{ CW(103, 1), 0x00, 0x04 }, //CW103_1 [7:0] 4 //FB_19K2[2:0]
{ CW(103, 0), 0x00, 0x20 }, //CW103_0 [7:0] 32 //IBAND_19K2[5:0]
#if defined REF_CLK_32K //==============================================
{ CW( 3, 0), 0x1F, 0x20 }, //CW3_0 [7:5] 1,
#elif defined REF_CLK_13M
{ CW( 3, 0), 0x1F, 0x40 }, //CW3_0 [7:5] 2,
#elif defined REF_CLK_26M
{ CW( 3, 0), 0x1F, 0xC0 }, //CW3_0 [7:5] 6,
#endif //=================================================================
#if defined REF_CLK_32K //==============================================
{ CW( 2, 1), 0xBF, 0x40 }, //CW2_1 [6:6] 1 //INSEL
#else
{ CW( 2, 1), 0xBF, 0x00 }, //CW2_1 [6:6] 0 //INSEL
#endif
{ CW( 5, 1), 0x7F, 0x00 }, //CW5_1 [7:7] 0 //PRE_CH
{ CW( 8, 0), 0xF7, 0x08 }, //CW8_0 [3:3] 1 //AFC_CAL
};
// end chip ID = 5
#define CAL_PRESET_COUNT 27
static const ctrl_word_operation CalPresetProcess[CAL_PRESET_COUNT] = {
{ CW( 14, 0), 0x7F, 0x00 }, //CW14_0 [7:7] 0 //S_AUTO,STEREO
{ CW( 14, 0), 0xEF, 0x10 }, //CW14_0 [4:4] 1
{ CW( 5, 1), 0xFB, 0x04 }, //CW5_1 [2:2] 1 //Window_L
{ CW( 3, 0), 0xF8, 0x05 }, //CW3_0 [2:0] 5 //AMP_P,S_DIV_3
{ CW( 3, 0), 0xFE, 0x01 }, //CW3_0 [0:0] 1 //S_DIV_256,S_DIV_128,S_DIV_3
{ CW( 3, 1), 0xE3, 0x1C }, //CW3_1 [4:2] 7 //ISEL
{ CW( 12, 0), 0xFE, 0x01 }, //CW12_0 [0:0] 1 //PLL19K_P
{ CW( 12, 0), 0xFD, 0x02 }, //CW12_0 [1:1] 1 //PLL_19K_P
{ CW( 7, 0), 0xE0, 0x17 }, //CW7_0 [4:0] 23 //VCO_PW,PRE_PW,LO_PW,VER
{ CW( 10, 1), 0xDF, 0x20 }, //CW10_1 [5:5] 1 //FRCKTEST
{ CW( 12, 1), 0xEF, 0x00 }, //CW12_1 [4:4] 0 //EN_TESTMODE_PLL19K
{ CW( 12, 1), 0x1F, 0x00 }, //CW12_1 [7:5] 0 //TEST_OUTSEL_19K[2:0]
{ CW( 6, 1), 0x0F, 0x10 }, //CW6_1 [7:4] 1 //TAR[3:0]
{ CW( 7, 1), 0xFC, 0x00 }, //CW7_1 [1:0] 0 //CAL[1:0]
{ CW( 97, 1), 0xE0, 0x10 }, //CW97_1 [4:0] 16 //FRTUNE1[4:0]
{ CW( 97, 0), 0xE0, 0x00 }, //CW97_0 [4:0] 0 //FRTUNE2[4:0]
{ CW( 98, 1), 0x00, 0x80 }, //CW98_1 [7:0] 128 //DMTUNE1I[7:0]
{ CW( 98, 0), 0x00, 0x00 }, //CW98_0 [7:0] 0 //DMTUNE2I[3:0]
{ CW( 99, 1), 0x00, 0x80 }, //CW99_1 [7:0] 128 //DMTUNE1Q[7:0]
{ CW( 99, 0), 0xF0, 0x00 }, //CW99_0 [3:0] 0 //DMTUNE2Q[3:0]
{ CW(101, 0), 0xF8, 0x04 }, //CW101_0 [2:0] 4 //LPF[2:0]
{ CW(103, 1), 0x00, 0x04 }, //CW103_1 [7:0] 4 //FB_19K2[2:0]
{ CW(103, 0), 0x00, 0x20 }, //CW103_0 [7:0] 32 //IBAND_19K2[5:0]
#if defined REF_CLK_32K //==============================================
{ CW( 3, 0), 0x1F, 0x20 }, //CW3_0 [7:5] 1,
#elif defined REF_CLK_13M
{ CW( 3, 0), 0x1F, 0x40 }, //CW3_0 [7:5] 2,
#elif defined REF_CLK_26M
{ CW( 3, 0), 0x1F, 0xC0 }, //CW3_0 [7:5] 6,
#endif //=================================================================
#if defined REF_CLK_32K //==============================================
{ CW( 2, 1), 0xBF, 0x40 }, //CW2_1 [6:6] 1 //INSEL
#else
{ CW( 2, 1), 0xBF, 0x00 }, //CW2_1 [6:6] 0 //INSEL
#endif
{ CW( 5, 1), 0x7F, 0x00 }, //CW5_1 [7:7] 0 //PRE_CH
{ CW( 8, 0), 0xF7, 0x08 }, //CW8_0 [3:3] 1 //AFC_CAL
};
#define CAL_PLL_COMMAND_COUNT 21
static const ctrl_word_operation CalPLLProcess[CAL_PLL_COMMAND_COUNT] = {
{ CW( 12, 1), 0xFC, 0x03 }, //CW12_1 [1:0] 3
{ CW( 6, 0), 0xFC, 0x01 }, //CW6_0 [1:0] 1 //WIN_S[1:0],set window source
{ CW( 7, 1), 0xFC, 0x03 }, //CW7_1 [1:0] 3 //CAL[1:0],Enable calibration
{ CW( 6, 1), 0x00, 0x66 }, //CW6_1 [7:0] 102 //CNT_S, set clock source
{ CW( 25, 1), 0x00, 0x03 }, //CW25_1 [7:0] 3 //CNT_T[11:8], set target value
#if defined REF_CLK_32K //==============================================
{ CW( 25, 0), 0x00, 0x7A }, //CW25_0 [7:0] 122 //CNT_T[7:0], set target value
#elif defined REF_CLK_13M
{ CW( 25, 0), 0x00, 0x5E }, //CW25_0 [7:0] 94
#elif defined REF_CLK_26M
{ CW( 25, 0), 0x00, 0x5E }, //CW25_0 [7:0] 94
#endif //=================================================================
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all Flag register
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //WIN_EN, start calibration
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 6, 1), 0x00, 0x76 }, //CW6_1 [7:0] 118 //CNT_S, set clock source
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all Flag register
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //WIN_EN, start calibration
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 6, 1), 0x00, 0x56 }, //CW6_1 [7:0] 86 //CAL, Enable calibration
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all Flag register
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //WIN_EN, start calibration
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 12, 1), 0xF8, 0x04 }, //CW12_1 [2:0] 4 //Set Divided vaule=24 and disable calibration mode of PLL19K
};
#define CAL_DEMOD_I_COMMAND_COUNT 31
static const ctrl_word_operation CalDemodIProcess[CAL_DEMOD_I_COMMAND_COUNT] = {
{ CW( 8, 0), 0xFD, 0x02 }, //CW8_0 [1:1] 1 //FM_CALI, Enalbe calibation mode of I channel demodulator
{ CW( 8, 0), 0xFB, 0x04 }, //CW8_0 [2:2] 1 //FM_CALQ, Enalbe calibation mode of Q channel demodulator
{ CW( 8, 0), 0xEF, 0x00 }, //CW8_0 [4:4] 0 //DEM_RSB, Reset demodulator
{ CW( 8, 0), 0xEF, 0x10 }, //CW8_0 [4:4] 1 //DEM_RSB, Reset demodulator
{ CW( 7, 1), 0xFC, 0x03 }, //CW7_1 [1:0] 3 //CAL[1:0], Enable calibraton process
{ CW( 6, 0), 0xFC, 0x01 }, //CW6_0 [1:0] 1 //WIN_S[1:0], Set window soure
{ CW( 6, 1), 0x00, 0xAA }, //CW6_1 [7:0] 170 //CNTS[2:0],TAR[3:0], Set clock source and traget register
#if defined REF_CLK_32K //==============================================
{ CW( 25, 0), 0x00, 0x45 }, //CW25_0 [7:0] 69 //CNT_T[7:0]
#elif defined REF_CLK_13M
{ CW( 25, 0), 0x00, 0x23 }, //CW25_0 [7:0] 35
#elif defined REF_CLK_26M
{ CW( 25, 0), 0x00, 0x23 }, //CW25_0 [7:0] 35
#endif //=================================================================
{ CW( 25, 1), 0x00, 0x04 }, //CW25_1 [7:0] 4+ //CNT_T[11:8]
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //WIN_EN, Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 6, 1), 0x00, 0xBA }, //CW6_1 [7:0] 186 //CNTS[2:0],TAR[3:0],Set clock source and traget register
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0, //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //WIN_EN, Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 6, 1), 0x00, 0xCC }, //CW6_1 [7:0] 204 //CNTS[2:0],TAR[3:0],Set clock source and traget register
#if defined REF_CLK_32K //==============================================
{ CW( 25, 0), 0x00, 0xDA }, //CW25_0 [7:0] 218 //CNT_T[7:0]
#elif defined REF_CLK_13M
{ CW( 25, 0), 0x00, 0xD4 }, //CW25_0 [7:0] 212
#elif defined REF_CLK_26M
{ CW( 25, 0), 0x00, 0xD4 }, //CW25_0 [7:0] 212
#endif //=================================================================
{ CW( 25, 1), 0x00, 0x00 }, //CW25_1 [7:0] 0+ //CNT_T[11:8]
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //WIN_EN, Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 6, 1), 0x0F, 0xD0 }, //CW6_1 [7:4] 13 //CNTS[2:0],TAR[3:0],Set clock source and traget register
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //WIN_EN,Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 8, 0), 0xF9, 0x00 }, //CW8_0 [2:1] 0 //FM_CALI,Q, disable I, Q calibration mode
};
// start chip ID = 5
#define CHANNEL_FILTER_COUNT 13
static const ctrl_word_operation ChannelFilter[CHANNEL_FILTER_COUNT] = {
{ CW( 10, 1), 0xFE, 0x01 }, //CW10_0 [0:0] 1 //Enable channel filter calibraton
{ CW( 7, 1), 0xFC, 0x03 }, //CW7_1 [1:0] 3 //Enable calibraton process
{ CW( 6, 0), 0xFC, 0x01 }, //CW6_0 [1:0] 1 //Set window soure
{ CW( 6, 1), 0x00, 0x28 }, //CW6_1 [7:0] 40 //Set clock ource and target register
{ CW( 25, 1), 0x00, 0x00 }, //CW25_1 [7:0] 0 //
{ CW( 25, 0), 0x00, 0x31 }, //CW25_0 [7:0] 49 //(Please set this field as an user-defined value on the control program)
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset CW1_0
{ CW( 6, 1), 0x0F, 0x10 }, //CW6_1 [7:4] 1 //Set clock source and target register
{ CW( 7, 1), 0xFC, 0x00 }, //CW7_1 [1:0] 0 //Disable calibration process
{ CW( 10, 1), 0xFE, 0x00 }, //CW10_1 [0:0] 0 //Disable channel filter calibraton
};
#define MUXOFF_MN_COUNT 24
static const ctrl_word_operation MuxOff_MN[MUXOFF_MN_COUNT] = {
{ CW( 8, 0), 0xFE, 0x00 }, //CW8_0 [0:0] 0 //Turn off Demod.
{ CW( 15, 0), 0xFD, 0x02 }, //CW15_0 [1:1] 1 //Enable MUX calibraton (MUX_CON_CAL)
{ CW( 11, 1), 0x3F, 0x80 }, //CW11_1 [7:6] 2 //Gain option (D2S_MODE, I2V_MODE)
{ CW( 14, 0), 0x6F, 0x00 }, //CW14_0 [7,4] //Force mono mode
{ CW( 11, 1), 0xFB, 0x00 }, //CW11_1 [2:2] 0 //Enable MUX mono calibration (ST_CAL)
{ CW( 18, 1), 0x3F, 0x80 }, //CW18_1 [7:6] 2 //Enable MUX L calibration (MUXLOFFCAL, TEST_LCH)
{ CW( 19, 1), 0x8F, 0x10 }, //CW19_1 [6:4] 1 //Enable MUX L calibration (MUXLOFFCAL, TEST_LCH)
{ CW( 14, 1), 0xFE, 0x00 }, //CW14_1 [0:0] 0 //Turn off AMP1
{ CW( 7, 1), 0xFC, 0x03 }, //CW7_1 [1:0] 3 //Enable calibraton process
{ CW( 6, 0), 0xFC, 0x01 }, //CW6_0 [1:0] 1 //Set window soure
{ CW( 6, 1), 0x00, 0x90 }, //CW6_1 [7:0] 144 //Set clock ource and target register
{ CW( 9, 0), 0xBF, 0x40 }, //CW9_0 [6:6] 1 //
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset
{ CW( 18, 1), 0x3F, 0x40 }, //CW18_1 [7:6] 1 //Enable MUX R calibration (MUXROFFCAL, TEST_RCH)
{ CW( 19, 1), 0x8F, 0x20 }, //CW19_1 [6:4] 2 //Enable MUX R calibration (MUXROFFCAL, TEST_RCH)
{ CW( 6, 1), 0x00, 0xA0 }, //CW6_1 [7:0] 160 //Set clock source and target register
{ CW( 9, 0), 0xBF, 0x40 }, //CW9_0 [6:6] 1 //
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset
};
#define MUXOFF_ST_COUNT 26
static const ctrl_word_operation MuxOff_ST[MUXOFF_ST_COUNT] = {
{ CW( 14, 0), 0x6F, 0x10 }, //CW14_0 [4:4] 1 //Force stereo mode
{ CW( 11, 1), 0xFB, 0x04 }, //CW11_1 [2:2] 1 //Enable MUX stereo calibration (ST_CAL)
{ CW( 18, 1), 0x3F, 0x80 }, //CW18_1 [7:6] 2 //Enable MUX L calibration (MUXLOFFCAL, TEST_LCH)
{ CW( 19, 1), 0x8F, 0x10 }, //CW19_1 [6:4] 1 //Enable MUX L calibration (MUXLOFFCAL, TEST_LCH)
{ CW( 6, 1), 0x00, 0xB0 }, //CW6_1 [7:0] 176 //Set clock source and target register
{ CW( 9, 0), 0xBF, 0x40 }, //CW9_0 [6:6] 1 //
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset
{ CW( 18, 1), 0x3F, 0x40 }, //CW18_1 [7:6] 1 //Enable MUX R calibration (MUXROFFCAL, TEST_RCH)
{ CW( 19, 1), 0x8F, 0x20 }, //CW19_1 [6:4] 2 //Enable MUX R calibration (MUXROFFCAL, TEST_RCH)
{ CW( 6, 1), 0x00, 0xC0 }, //CW6_1 [7:0] 192 //Set clock source and target register
{ CW( 9, 0), 0xBF, 0x40 }, //CW9_0 [6:6] 1 //
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset
{ CW( 6, 1), 0x0F, 0x10 }, //CW6_1 [7:4] 1 //Set clock source and target register
{ CW( 7, 1), 0xFC, 0x00 }, //CW7_1 [1:0] 0 //Disable calibration process
{ CW( 9, 0), 0xBF, 0x00 }, //CW9_0 [6:6] 0 //Resume to default value
{ CW( 18, 1), 0x3F, 0x00 }, //CW18_1 [7:6] 0 //Disable MUX calibration
{ CW( 19, 1), 0x8F, 0x00 }, //CW19_1 [6:4] 0 //Disable MUX calibration
{ CW( 11, 1), 0xFB, 0x00 }, //CW11_1 [2:2] 0 //Disable MUX stereo calibration (ST_CAL)
{ CW( 8, 0), 0xFE, 0x01 }, //CW8_0 [0:0] 1 //Turn on Demod.
{ CW( 14, 1), 0xFE, 0x01 }, //CW14_1 [0:0] 1 //Turn on AMP1
};
#define PFOSC_560K_COUNT 26
static const ctrl_word_operation Pfosc_560K[PFOSC_560K_COUNT] = {
{ CW( 10, 0), 0xFE, 0x01 }, //CW10_0 [0:0] 1 //Enable PTOSC calibraton and power on PTOSC
{ CW( 10, 0), 0xFD, 0x02 }, //CW10_0 [1:1] 1 //Enable PTOSC calibraton and power on PTOSC
{ CW( 10, 0), 0xFD, 0x00 }, //CW10_0 [1:1] 0 //Reset PTOSC
{ CW( 10, 0), 0xFD, 0x02 }, //CW10_0 [1:1] 1 //Reset PTOSC
{ CW( 6, 1), 0x00, 0xEE }, //CW6_1 [7:0] 238 //Set clock ource and target register
{ CW( 25, 1), 0x00, 0x04 }, //CW25_1 [7:0] 3+,4 //CNT_T[11:8]
#if defined REF_CLK_32K //==============================================
{ CW( 25, 0), 0x00, 0x46 }, //CW25_0 [7:0] 123,70 //CNT_T[7:0]
#elif defined REF_CLK_13M
{ CW( 25, 0), 0x00, 0x5E }, //CW25_0 [7:0] 94
#elif defined REF_CLK_26M
{ CW( 25, 0), 0x00, 0x5E }, //CW25_0 [7:0] 94
#endif //=================================================================
{ CW( 7, 1), 0xFC, 0x03 }, //CW7_0 [1:0] 3 //
{ CW( 3, 0), 0xEF, 0x10 }, //CW3_0 [4:4] 1 //
{ CW( 5, 1), 0x7F, 0x00 }, //CW5_1 [7:7] 0 //
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset
{ CW( 6, 1), 0x00, 0xFE }, //CW6_1 [7:0] 254 //Set clock source and target register
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset
{ CW( 6, 1), 0x0F, 0x10 }, //CW6_1 [7:4] 1 //Set clock source and target register
{ CW( 7, 1), 0xFC, 0x00 }, //CW7_1 [1:0] 0 //Disable calibration process
{ CW( 3, 0), 0xEF, 0x00 }, //CW3_0 [4:4] 0 //Disable RFPLL calibration mode
{ CW( 5, 1), 0x7F, 0x80 }, //CW5_1 [7:7] 1 //PRE_CH=1
{ CW( 3, 0), 0xEF, 0x10 }, //CW3_0 [4:4] 1 //CAL_PLL=1
#if defined (__MT6188CR_DISABLE_SOFTMUTE__)
{ CW( 14, 0), 0xF7, 0x00 }, //CW14_0 [3:3] 1 //SMUTE=1
#else
{ CW( 14, 0), 0xF7, 0x08 }, //CW14_0 [3:3] 1 //SMUTE=1
#endif
{ CW( 34, 0), 0xFE, 0x01 }, //CW34_0 [0:0] 1 //
};
#define SM_CAL_OFFSET_COUNT 20
static const ctrl_word_operation SM_Cal_Offset[SM_CAL_OFFSET_COUNT] = {
{ CW( 22, 1), 0xFE, 0x01 }, //CW22_1 [0:0] 1 //
{ CW( 17, 1), 0x7F, 0x00 }, //CW17_1 [7:7] 0 //
{ CW( 18, 0), 0xF7, 0x00 }, //CW18_0 [3:3] 0 //
{ CW( 18, 1), 0xF7, 0x00 }, //CW18_1 [3:3] 0 //
{ CW( 6, 1), 0x0F, 0x10 }, //CW6_1 [7:4] 1 //Set clock source and target register
{ CW( 7, 1), 0xFC, 0x00 }, //CW7_1 [1:0] 0 //Disable calibration process
{ CW(101, 1), 0xF0, 0x08 }, //CW101_1 [3:0] 8 //
{ CW( 19, 0), 0xFD, 0x02 }, //CW19_0 [1:1] 1 //Enable and wait 20ms
{ CW( 7, 1), 0xFC, 0x03 }, //CW7_1 [1:0] 3 //Enable calibration process
{ CW( 6, 1), 0x00, 0x40 }, //CW6_1 [7:0] 64 //Set clock source and target register
{ CW( 9, 0), 0xBF, 0x00 }, //CW9_0 [6:6] 0 //
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
{ CW(127, 1), 0x00, 0x01 }, // <----------------- polling SARIFG
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //reset
{ CW( 6, 1), 0x0F, 0x10 }, //CW6_1 [7:4] 1 //Set clock source and target register
{ CW( 7, 1), 0xFC, 0x00 }, //CW7_1 [1:0] 0 //Disable calibration process
{ CW( 9, 0), 0xBF, 0x00 }, //CW9_0 [6:6] 0 //Resume to default value
{ CW( 19, 0), 0xFD, 0x00 }, //CW19_0 [1:1] 0 //
{ CW( 22, 1), 0xFE, 0x00 }, //CW22_1 [0:0] 0 //
};
#define SM_CAL_SLOPE_COUNT 20
static const ctrl_word_operation SM_Cal_Slope[SM_CAL_SLOPE_COUNT] = {
{ CW( 22, 1), 0xFE, 0x01 }, //CW22_1 [0:0] 1 //
{ CW( 17, 1), 0x7F, 0x00 }, //CW17_1 [7:7] 0 //
{ CW( 18, 0), 0xF7, 0x08 }, //CW18_0 [3:3] 1 //
{ CW( 18, 1), 0xF7, 0x00 }, //CW18_1 [3:3] 0 //
{ CW( 19, 0), 0xFC, 0x03 }, //CW19_0 [1:0] 3 //
{ CW( 6, 1), 0x00, 0x80 }, //CW6_1 [7:0] 128 //Set clock source and target register
{ CW( 9, 0), 0xBF, 0x40 }, //CW9_0 [6:6] 1 //
{ CW( 7, 1), 0xFC, 0x03 }, //CW7_1 [1:0] 3 //Enable calibration process
{ CW( 1, 0), 0x00, 0x00 }, //CW1_0 [7:0] 0 //Clear all FLG registers
{ CW( 6, 1), 0xFE, 0x01 }, //CW6_1 [0:0] 1 //Start calibration process
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