fifo.vhd

fifo example vhdl code

-------------------------------------------------------------------------------
-- Project     : Journal 2 - Async fifo
--             : Integrated Broadband Electronics. Course 34349 @ DTU/Denmark
-------------------------------------------------------------------------------
-- File        : fifo.vhd
-- Author      : Philip S鴈berg ([e-mail])
-------------------------------------------------------------------------------
-- Description : top-level entity for async fifo thingy
-------------------------------------------------------------------------------
-- Revision    : 1.0     17/12/2005      Initial version
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity async_fifo is
	port (
		reset			: in std_logic;
		wclk			: in std_logic;
		rclk			: in std_logic;
		write_enable	: in std_logic;
		read_enable		: in std_logic;
--		fifo_occu_in	: out std_logic_vector(4 downto 0);	--I will provide empty and full signals, which I assume these are for?
--		fifo_occu_out	: out std_logic_vector(4 downto 0);
		empty			: out std_logic;
		full			: out std_logic;
		write_data_in	: in std_logic_vector(7 downto 0);
		read_data_out	: out std_logic_vector(7 downto 0)
	);
end async_fifo;

Architecture RTL of async_fifo is

component control is
	port (
		reset : in std_logic;		--asyn reset
		rdclk : in std_logic;		--read clock
		wrclk : in std_logic;		--write clock
		fifo_wr : in std_logic;		--write request signal
		fifo_rd : in std_logic;		--read request signal
		valid_rd : out std_logic;	--synchronized write request signal
		valid_wr : out std_logic;	--synchronized read request signal
		rd_ptr : out std_logic_vector(2 downto 0);	--read pointer (binary)
		wr_ptr : out std_logic_vector(2 downto 0);	--write pointer (binary)
		empty : out std_logic;		--empty signal
		full : out std_logic		--full signal
	);
end component;

component memory IS
	port (
	addra: IN std_logic_VECTOR(2 downto 0);
	addrb: IN std_logic_VECTOR(2 downto 0);
	clka: IN std_logic;
	clkb: IN std_logic;
	dina: IN std_logic_VECTOR(7 downto 0);
	doutb: OUT std_logic_VECTOR(7 downto 0);
	wea: IN std_logic);
END component;

signal adr_read : std_logic_vector(2 downto 0);
signal adr_write : std_logic_vector(2 downto 0);
--signal req_read : std_logic;
signal req_write : std_logic;

signal not_used_0 : std_logic;

begin

control0 : control
port map (
	reset		=> reset			,
	rdclk       => rclk             ,
	wrclk       => wclk             ,
	fifo_wr     => write_enable     ,
	fifo_rd     => read_enable      ,
	valid_rd    => not_used_0       ,
	valid_wr    => req_write        ,
	rd_ptr      => adr_read         ,
	wr_ptr      => adr_write        ,
	empty       => empty	        ,
	full        => full
);

memory0 : memory
port map (
	addra		=> adr_write		,
	addrb       => adr_read         ,
	clka        => wclk             ,
	clkb        => rclk             ,
	dina        => write_data_in    ,
	doutb       => read_data_out    ,
	wea         => req_write
);

end RTL;