syslib.c

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        return (ERROR);

    retVal = sysFlashGet (string, strLen, offset);
    string [strLen] = EOS;

    return (OK);
    }

/******************************************************************************
*
* sysNvRamSet - write to non-volatile RAM
*
* This routine copies a specified string into non-volatile RAM.
*
* RETURNS: OK, or ERROR if access is outside the non-volatile RAM range.
*
* SEE ALSO: sysNvRamGet()
*/

STATUS sysNvRamSet
    (
    char *string,     /* string to be copied into non-volatile RAM */
    int strLen,       /* maximum number of bytes to copy           */
    int offset        /* byte offset into non-volatile RAM         */
    )

    {
    offset += NV_BOOT_OFFSET;   /* boot line begins at <offset> = 0 */

    if ((offset < 0)
     || (strLen < 0)
     || ((offset + strLen) > NV_RAM_SIZE))
        return ERROR;

    NV_RAM_WR_ENBL;

    return (sysFlashSet (string, strLen, offset));

    }

/******************************************************************************
*
* sysFlashBoardDelay - create a delay
*
* This routine is used by flashMem.c to produce specified delays. It
* appears that the Flash driver cannot use taskDelay() at certain
* points.
*
* RETURNS: N/A
*/

void sysFlashBoardDelay (void)
    {
    return;
    }
#endif /* INCLUDE_FLASH */


#ifdef INCLUDE_CACHE_SUPPORT

/******************************************************************************
*
* s3c44bCacheLibInit - initialize ARM cache library function pointers
*
* This routine initializes the cache library for SNG32C processor.  It
* initializes the function pointers and configures the caches to the
* specified cache modes.  Modes should be set before caching is
* enabled.  If two complementary flags are set (enable/disable), no
* action is taken for any of the input flags.
*
* INTERNAL
* This routine is called (from cacheLibInit()), before sysHwInit has
* been called, and before BSS has been cleared.
*
* RETURNS: OK always
*
*/

STATUS s3c44bCacheLibInit
    (
    CACHE_MODE    instMode,    /* instruction cache mode */
    CACHE_MODE    dataMode    /* data cache mode */
    )
    {

#if ((ARMCACHE == ARMCACHE_S3C44B0X))
    cacheLib.enableRtn               = (FUNCPTR) s3c44bCacheEnable;
    cacheLib.disableRtn              = (FUNCPTR) s3c44bCacheDisable;
    cacheLib.flushRtn                = (FUNCPTR) s3c44bCacheFlush;
    cacheLib.invalidateRtn           = (FUNCPTR) NULL;
    cacheLib.clearRtn                = (FUNCPTR) NULL;
    cacheLib.textUpdateRtn           = (FUNCPTR) NULL;
    cacheLib.pipeFlushRtn            = (FUNCPTR) NULL;
    cacheLib.dmaMallocRtn            = (FUNCPTR) NULL; /* s3c44bCacheDmaMalloc;*/
    cacheLib.dmaFreeRtn              = (FUNCPTR) NULL; /* s3c44bCacheDmaFree; */
    s3c44bCacheFuncs.virtToPhysRtn = (FUNCPTR) NULL; /* s3c44bVirtToPhysRtn; */
    s3c44bCacheFuncs.physToVirtRtn = (FUNCPTR) NULL; /* s3c44bPhysToVirtRtn; */

    if (
    (instMode & CACHE_WRITEALLOCATE)    ||
    (dataMode & CACHE_WRITEALLOCATE)    ||
    (instMode & CACHE_NO_WRITEALLOCATE)    ||
    (dataMode & CACHE_NO_WRITEALLOCATE)    ||
    (instMode & CACHE_SNOOP_ENABLE)        ||
    (dataMode & CACHE_SNOOP_ENABLE)        ||
    (instMode & CACHE_SNOOP_DISABLE)    ||
    (dataMode & CACHE_SNOOP_DISABLE)    ||
    (instMode & CACHE_BURST_ENABLE)        ||
    (dataMode & CACHE_BURST_ENABLE)        ||
    (instMode & CACHE_BURST_DISABLE)    ||
    (dataMode & CACHE_BURST_DISABLE))
        return ERROR;

    /* This has combined Instruction and Data caches */
    if (instMode != dataMode)
        return ERROR;

#else
#error ARMCACHE type not supported here
#endif


    return OK;
    }

/******************************************************************************
*
* s3c44bCacheDmaMalloc - allocate a cache-safe buffer
*
* This routine attempts to return a pointer to a section of memory
* that will not experience cache coherency problems.  This routine
* is only called when MMU support is available for cache control.
*
* RETURNS: A pointer to a cache-safe buffer, or NULL.
*
* SEE ALSO: s3c44bCacheDmaFree(), cacheDmaMalloc()
*
* NOMANUAL
*/

void * s3c44bCacheDmaMalloc
    (
    size_t    bytes    /* size of cache-safe buffer */
    )
    {
    void   *ptr;
   
    ptr = malloc (bytes);

    return (ptr);

    } /* cacheArchDmaMalloc() */

/******************************************************************************
*
* s3c44bCacheDmaFree - free the buffer acquired by cacheArchDmaMalloc()
*
* This routine returns to the free memory pool a block of memory previously
* allocated with cacheArchDmaMalloc().  The buffer is marked cacheable.
*
* RETURNS: OK, or ERROR if cacheArchDmaMalloc() cannot be undone.
*
* SEE ALSO: s3c44bCacheDmaMalloc(), cacheDmaFree()
*
* NOMANUAL
*/

STATUS s3c44bCacheDmaFree
    (
    void *    pBuf        /* ptr returned by cacheArchDmaMalloc() */
    )
    {

    free (pBuf);    /* free buffer after modified */

    return OK;

    } /* cacheArchDmaFree() */

/******************************************************************************
*
* s3c44bCacheEnable - enable cache
*
* This routine enables cache
*
* RETURNS: void
*
* SEE ALSO: s3c44bCacheDisable(), s3c44bCacheFlush()
*
* NOMANUAL
*/

void s3c44bCacheEnable
    ( 
    void
    )
    {

    UINT32    result;

    /* Clear cache-related bits */
    SBCARM7_CTRL_REG_READ (S3C44B_SYSCFG, result);

    result &= 0xF0;
    

#if (SBCARM7_CACHE_SIZE == S3C44B_CACHE_4K)
    result |=  S3C44B_WRITE_BUFF;        /* For 4K Cache */
    SBCARM7_CTRL_REG_WRITE (S3C44B_SYSCFG, result );
    s3c44bCacheFlush();
    SBCARM7_CTRL_REG_READ (S3C44B_SYSCFG, result);
    SBCARM7_CTRL_REG_WRITE (S3C44B_SYSCFG, (result | S3C44B_CACHE_4K ));
#endif /* (SBCARM7_CACHE_SIZE == S3C44B_CACHE_4K) */

#if (SBCARM7_CACHE_SIZE == S3C44B_CACHE_8K)	
     result |=  S3C44B_WRITE_BUFF;        /* Clear mode bits */
    SBCARM7_CTRL_REG_WRITE (S3C44B_SYSCFG, result);
    s3c44bCacheFlush();
    SBCARM7_CTRL_REG_READ (S3C44B_SYSCFG, result);
    SBCARM7_CTRL_REG_WRITE(S3C44B_SYSCFG, (result | S3C44B_CACHE_8K ));
#endif /* (SBCARM7_CACHE_SIZE == S3C44B_CACHE_8K) */
    }


/******************************************************************************
*
* s3c44bCacheDisable - disable cache
*
* This routine disables cache
*
* RETURNS: void
*
* SEE ALSO: s3c44bCacheEnable(), s3c44bCacheFlush()
*
* NOMANUAL
*/

void s3c44bCacheDisable
    (
    void
    )
    {
    UINT32 result;

    SBCARM7_CTRL_REG_READ(S3C44B_SYSCFG, result);
    SBCARM7_CTRL_REG_WRITE(S3C44B_SYSCFG,
                           (result & ~(S3C44B_CACHE_ENABLE)));
    }

/******************************************************************************
*
* s3c44bCacheFlush - flush the cache
*
* This routine flushes the cache
*
* RETURNS: void
*
* SEE ALSO: s3c44bCacheEnable(), s3c44bCacheDisable()
*
* NOMANUAL
*/

void s3c44bCacheFlush(void)
    {
    int i;
    UINT32 *tagram, *lru;

    tagram = (UINT32 *)S3C44B_TAGRAM;
    lru =  (UINT32 *)S3C44B_LRU;
    s3c44bCacheDisable();

    for(i=0; i < 128; i++) 
        {
        *lru = 0x00000000; 
        lru += 0x10;
        }
    
    for(i=0; i < (128*4); i++) 
        {
        *tagram = 0x00000000; 
        tagram += 0x10;
        }
    
    }

/******************************************************************************
*
* s3c44bPhysToVirtRtn - force memory to cacheable region
*
* This routine clears the "non-cache" bit on an address to force it to use
* the cacheable region of memory
*
* RETURNS: void
*
* SEE ALSO: s3c44bCacheEnable(), s3c44bCacheDisable()
*
* NOMANUAL
*/

void * s3c44bPhysToVirtRtn 
    (
    void *adrs
    )

    {
        return adrs;
    }

/******************************************************************************
*
* s3c44bVirtToPhysRtn - force memory to non-cacheable region
*
* This routine sets the "non-cache" bit on an address to force it to use
* the non-cacheable region of memory
*
* RETURNS: void
*
* SEE ALSO: s3c44bCacheEnable(), s3c44bCacheDisable()
*
* NOMANUAL
*/

void * s3c44bVirtToPhysRtn 
    (
    void *adrs
    )
    
    {
        return adrs;
    }

#endif    /* INCLUDE_CACHE_SUPPORT */

#ifdef DEBUG
/******************************************************************************
*
* sysDebug - print message using polled serial driver
*
* Use the polled driver to print debug messages.  Useful before the full
* hardware initialization is complete (but only after sysHwInit).
*
* RETURNS: N/A.
*
* NOMANUAL
*/

void sysDebug
    (
    char *str
    )
    {
    int msgSize;
    int msgIx;
    LOCAL SIO_CHAN * pSioChan;        /* serial I/O channel */
    LOCAL BOOL beenHere = FALSE;

    msgSize = strlen (str);

    if (!beenHere)
        {
        sysSerialHwInit ();

        pSioChan = sysSerialChanGet (0);

      sioIoctl (pSioChan, SIO_BAUD_SET, (void *)CONSOLE_BAUD_RATE);

        sioIoctl (pSioChan, SIO_MODE_SET, (void *) SIO_MODE_POLL);

        beenHere = TRUE;
	}

    for (msgIx = 0; msgIx < msgSize; msgIx++)
        {
        while (sioPollOutput (pSioChan, str[msgIx]) == EAGAIN)
            /* do nothing */;
        }
    }
#endif /* DEBUG */

void s3cExcVecSet(void)
{
    int i;
    i = (int)&excEnterUndef;
    *((volatile int*)(S3C_EXC_BASE + 0x0)) = i;

    i = (int)&excEnterSwi;
    *((volatile int*)(S3C_EXC_BASE + 0x4)) = i;

    i = (int)&excEnterPrefetchAbort;
    *((volatile int*)(S3C_EXC_BASE + 0x8)) = i;

    i = (int)&excEnterDataAbort;
    *((volatile int*)(S3C_EXC_BASE + 0xc)) = i;

    i = (int)&intEnt;
    *((volatile int*)(S3C_EXC_BASE + 0x14)) = i;

    return;
    
}

void s3cPortInit(void)
{
    /* 
    CAUTION:Follow the configuration order for setting the ports. 
    1) setting value 
    2) setting control register 
    3) configure pull-up resistor.
    */
    /* port A 10bits in all
    bit9-0 is configured as ADDR24-16,ADDR0 respectively */
    S3C44B_REG_WRITEW(S3C44B_PCONA, 0x3ff);

    /* port B 11bits in all
    bit 10  9  8  7  6  5  4  3  3  1  0
         0  0  1  1  1  0  0  1  1  1  1_ SCKE,sdram
         |  |  |  |  |  |  |  |  |  |_ SCLK,sdram
         |  |  |  |  |  |  |  |  |_ nSCAS:nCAS2   
         |  |  |  |  |  |  |  |_ nSRAS:nCAS3
         |  |  |  |  |  |  |_ nWBE2:nBE2:DQM2, NC(not connected)
         |  |  |  |  |  |_ nWBE3:nBE3:DQM3, NC (not connected)
         |  |  |  |  |_ nGCS1, nand flash
         |  |  |  |_ nGCS2, usb
         |  |  |_ nGCS3, RTL8019
         |  |_ nGCS4, NC
         |_ nGCS5, NC
         
    */
     S3C44B_REG_WRITEW(S3C44B_PDATB, 0x1ff);
/*     S3C44B_REG_WRITEW(S3C44B_PCONB, 0x1cf);*/
     S3C44B_REG_WRITEW(S3C44B_PCONB, 0x1ff);

     /* port c 16bits in all BUSWIDTH=16
     PCONC:
         PC15  PC14  PC13  PC12  PC11  PC10  PC09  PC08
          01    01    11    11    01    01    01   01
         out    out   RxD1  TxD1  out   out   out  out
          NC    NC    UART1 UART1  NC    NC    NC  NC 
         PC07  PC06  PC05  PC04  PC03  PC02  PC01  PC00
          01    01    01    01    01    01    01   00
          out   out   out   out   out   out   out  in
          NC    NC    NC    NC   nand  nand  nand  nand
                                  ALE   CLE   CE   RB
     */ 
	 
    /* S3C44B_REG_WRITEW(S3C44B_PDATC, 0x0001);
     S3C44B_REG_WRITEW(S3C44B_PCONC, 0x5f555554);
     S3C44B_REG_WRITEW(S3C44B_PUPC, 0x3000);
     */
     S3C44B_REG_WRITEW(S3C44B_PDATC, 0xffff);
     S3C44B_REG_WRITEW(S3C44B_PCONC, 0x0f000054);
     S3C44B_REG_WRITEW(S3C44B_PUPC, 0x3000);

     /* port d 8bits in all LCD control
     PCOND:
         PD07  PD06  PD05  PD04  PD03  PD02  PD01  PD00
         10     10    10    10    10    10    10    10
        VFRAME  VM   VLINE VCLK  VD3   VD2   VD1   VD0
     */
     /* These pins must be set only after CPU's internal LCD controller is enable*/
    /* S3C44B_REG_WRITEW(S3C44B_PDATD, 0x55);
     S3C44B_REG_WRITEW(S3C44B_PCOND, 0xaaaa);
     S3C44B_REG_WRITEW(S3C44B_PUPD, 0x0);
     */
     S3C44B_REG_WRITEW(S3C44B_PDATD, 0xff);
     S3C44B_REG_WRITEW(S3C44B_PCOND, 0x5555);
     S3C44B_REG_WRITEW(S3C44B_PUPD, 0x0);

     /* port e 9 bits in all 
     PCONE:
         PE08
          00
         endian(reserved)
         PE07  PE06  PE05  PE04  PE03  PE02  PE01  PE00
           01   01    01    01    01    10    10    11
           out  out  out   out    out  RxD0  TxD0  Fout
          LED3 LED2  LED1  LED0  Beep  UART0 UART0 clk
          0=ON 0=ON  0=ON  0=ON  1=ON
         */    
   /* 
     S3C44B_REG_WRITEW(S3C44B_PDATE, 0x3a7);
     S3C44B_REG_WRITEW(S3C44B_PCONE, 0x556b);
     S3C44B_REG_WRITEW(S3C44B_PUPE, 0x6);
*/
     S3C44B_REG_WRITEW(S3C44B_PDATE, 0x1ff);
     S3C44B_REG_WRITEW(S3C44B_PCONE, 0x5569);
     S3C44B_REG_WRITEW(S3C44B_PUPE, 0x6);
     /*
     port f 9bits 
     PCONF:
        PF08
        100
        IISCLK
        PF07  PF06  PF05      PF04   PF03   PF02   PF01   PF00
        100   001   001       00     01     01     10     10
        IISDI IISD0 IISLCRCK  output output output IICSDA IICSCL
     */
   /*  S3C44B_REG_WRITEW(S3C44B_PDATF, 0x0);
     S3C44B_REG_WRITEW(S3C44B_PCONF, 0x22445a);
     S3C44B_REG_WRITEW(S3C44B_PUPF, 0x1d3);
*/
     S3C44B_REG_WRITEW(S3C44B_PDATF, 0x3f);
     S3C44B_REG_WRITEW(S3C44B_PCONF, 0x0024900a);
     S3C44B_REG_WRITEW(S3C44B_PUPF, 0x1e3);
     /* port g */
     S3C44B_REG_WRITEW(S3C44B_PDATG, 0xff);
     S3C44B_REG_WRITEW(S3C44B_PDATG, 0xffff);
     S3C44B_REG_WRITEW(S3C44B_PUPG, 0x00);

     /* spucr D15-D0 pull up is disabled */
     S3C44B_REG_WRITEW(S3C44B_SPUCR, 0x7);
    /* S3C44B_REG_WRITEW(S3C44B_EXTINT, 0x0);*/
     S3C44B_REG_WRITEW(S3C44B_EXTINT, 0x44444444);

/*    S3C44B_REG_WRITEW(S3C44B_SYSCFG, 0x80);*/
     
    return;
}