rominit.s

vxworks bsp,s3c2410的vxworks开发资料

/* romInit.s - Samsung S3C44B0X ARM7 ROM initialization module */

/* Copyright Haifeng(David),Jing */

/*
modification history
--------------------
2004-FEB-20, jhf  modified from SBC ARM7 template.
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.  The entry
point, romInit(), is the first code executed on power-up.  It performs
the minimal setup needed to call the generic C routine romStart() with
parameter BOOT_COLD.

romInit() masks interrupts in the processor and the interrupt
controller and sets the initial stack pointer (to STACK_ADRS which is
defined in configAll.h).  Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.

The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot".  This
entry point allows a parameter to be passed to romStart().

NOTE:
ROM_WARM_ADRS is 24 bytes offset of romInit, for 20 bytes are for
exception vectors

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
.I "Samsung S3C44B0X User's Manual,"
*/

#define    _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "arch/arm/arm.h"
#include "arch/arm/mmuArmLib.h"
#include "config.h"
#include "regs.h"    

    .data
    .globl   FUNC(copyright_wind_river)
    .long    FUNC(copyright_wind_river)

/* internals */

    .globl    FUNC(romInit)    /* start of system code */
    /*
    .globl    FUNC(romUndef)
    .globl    FUNC(romSwi)
    .globl    FUNC(romPrefetch)
    .globl    FUNC(romReserved)
    .globl    FUNC(romIRQ)
    .globl    FUNC(romFIQ)
    */
    .globl    FUNC(sdata)      /* start of data */
    .globl    _sdata
/* sdata = start of data */
/* edata = end of data */
/* externals */

    .globl    FUNC(romStart)    /* system initialization routine */

_sdata:
FUNC_LABEL(sdata)
    .asciz    "start of data"
    .balign    4

    .text
    .balign 4    

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType    /@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit: 
    B       cold
    B       _romUndef
    B       _romSwi
    B       _romPrefetch
    B       _romDataAbort
    B       _romReserved              /* _romReserved */
    B       _romIRQ
    B       _romFIQ              /* _romFIQ     */
cold:
    MOV    r0, #BOOT_COLD    /* fall through to warm boot entry */
warm:
    B    start

    /* copyright notice appears at beginning of ROM (in TEXT segment) */

    .ascii   "Copyright 1984-2001 Wind River Systems, Inc."
    .balign 4

start:
    /* disable interrupts in CPU and switch to SVC32 mode */

    MRS    r1, cpsr
    BIC    r1, r1, #MASK_MODE
    ORR    r1, r1, #MODE_SVC32 | I_BIT | F_BIT
    MSR    cpsr, r1

    MOV    r13, r0    /* Save starttype in r13 so that r0 can be used for other purposes */

    /* disable watch dog */
    LDR	    r2, =S3C44B_WTCON	    /* watch dog disable */
    LDR	    r1, =0x0 		
    str	    r1, [r2] 

    /*
     * CPU INTERRUPTS DISABLED
     *
     * disable individual interrupts in the interrupt controller
     */

    LDR    r2, =S3C44B_INTMASK   
    LDR    r1, =0x07ffffff     /* all interrupt disable */    
    STR    r1, [r2]            /* disable all interrupt sources */


    /*	Set clock control registers */
    ldr	   r2, =S3C44B_INTCON
    ldr	   r1, =0x7
    str	   r1,[r2]

    /*	Set clock control registers */
    ldr	   r2, =S3C44B_LOCKTIME
    ldr	   r1, =0xfff
    str	   r1,[r2]

    /* PLL setting */
    ldr	   r2,  =S3C44B_PLLCON			           
	ldr	   r1,  =((M_DIV<<12)+(P_DIV<<4)+S_DIV)	/* Fin=8MHz,Fout=64MHz */
	str	   r1,  [r2]

    ldr	   r2, =S3C44B_CLKCON		 
    ldr	   r1, =0x7ff8	        /* All unit block CLK enable */
    str	   r1,[r2]

    /* syscfg */
    ldr    r2, =S3C44B_SYSCFG
    ldr    r1, =0x8
    str    r1, [r2]

    /* non cable area */
    ldr    r2, =S3C44B_NCACH_BE0
    ldr    r1, =0xc0000000
    str    r1, [r2]
#if 0
    ldr    r2, =S3C44B_NCACH_BE1
    ldr    r1, =0x02000000
    str    r1, [r2]
#endif    
    

    /* change BDMACON reset value for BDMA */
#if 0    
    ldr    r2, =S3C44B_BDIDES0       
    ldr    r1, =0x40000000      /* BDIDESn reset value should be 0x40000000 */
    str    r1, [r2]

    ldr    r2, =S3C44B_BDIDES1      
    ldr    r1, =0x40000000     /* BDIDESn reset value should be 0x40000000	*/
    str    r1, [r2]
#endif    
    /*
     * If not BOOT_COLD, bypass memory configuration, memory region
     * switching etc.
     */
    CMP    r0, #BOOT_COLD
    BNE    HiPosn

    /*
     * We are now executing in the normal (higher, still in ROM)
     * position in the memory map.  Remap memory to post-reset state,
     * so that the ROM is not now dual-mapped to zero upwards, but
     * RAM is mapped from zero, instead.
     */

    MOV    r0, #DRAM_TYPE  /* R0-> DRAM type */
    CMP    r0, #0x01       /* SDRAM = 0x01, EDO DRAM = 0x00 */
    BNE    EDO_RAM

SYNC_DRAM:
    /*
    LDR    r0, L$_SBCARM7Syscfg
    LDR    r1, L$_SysCfgSdram
    STR    r1, [r0]             
    */ /* Cache,WB disable */

/* ROM and RAM Configuration(Multiple Load and Store).  Multiple load
 * LDMIA instruction cannot be used as there is no way to load the
 * address L$_SystemInitDataSDRAM into a register (LDR Rn,=sym is broken)
 */
 

    LDR    r1, L$_SystemInitDataSDRAM 
    LDR    r2, L$_SystemInitDataSDRAM + 0x04
    LDR    r3, L$_SystemInitDataSDRAM + 0x08
    LDR    r4, L$_SystemInitDataSDRAM + 0x0c
    LDR    r5, L$_SystemInitDataSDRAM + 0x10
    LDR    r6, L$_SystemInitDataSDRAM + 0x14
    LDR    r7, L$_SystemInitDataSDRAM + 0x18
    LDR    r8, L$_SystemInitDataSDRAM + 0x1c
    LDR    r9, L$_SystemInitDataSDRAM + 0x20
    LDR    r10,L$_SystemInitDataSDRAM + 0x24
    LDR    r11,L$_SystemInitDataSDRAM + 0x28
    LDR    r12,L$_SystemInitDataSDRAM + 0x2c
    LDR    r0, =0x01c80000         
    STMIA  r0, {r1-r12}

    LDR    r1, L$_SystemInitDataSDRAM + 0x30
    LDR    r0, =0x01c80030
    STR    r1, [r0]

    
/*=============================================================
 * Copy to DRAM the section of ROM in which we are currently executing.
 * Soon, we will set the base pointer of DRAM to where the base pointer of
 * ROM used to be.  At that point the PC will suddenly be set in RAM and
 * must have legitimate code to execute.
 *=============================================================
 */

    LDR    PC, L$_HiPosn      

EDO_RAM:
    /* 
    because we don't support EDO ram, so we do nothing here
    jhf
    */
    B . /* dead here maybe light some LED */

HiPosn:
    MOV    r0, r13        /* restore starttype to r0 from r13 */
    LDR    sp, L$_STACK_ADDR_ROM
    MOV    fp, #0            /* zero frame pointer */

    /* jump to C entry point in ROM: routine - entry point + ROM base */

#if    (CPU == ARMARCH4_T)
    LDR    r12, L$_rStrtInRom
    ORR    r12, r12, #1        /* force Thumb state */
    BX     r12
#else
    LDR    pc, L$_rStrtInRom
#endif    /* (CPU == ARMARCH4_T) */

/*
;; ====================================================================
;; Name:	ROM_FIQ
;; Function:	This routine helps to pass control to proper FIQ handler
;;		once a FIQ interrupt occurs
;; ====================================================================	
*/
_ARM_FUNCTION(romFIQ)
_romFIQ:
	sub	sp, sp, #4
	stmfd	sp!, {r0}
	ldr	r0, L$_promFIQ         
	ldr	r0, [r0]
	str	r0, [sp, #4]
	ldmfd	sp!, {r0, pc}
/*	
;; ====================================================================
;; Name:	ROM_IRQ
;; Function:	This routine helps to pass control to proper IRQ handler
;;		once an IRQ interrupt occurs
;; ====================================================================	
*/
_ARM_FUNCTION(romIRQ)
_romIRQ:    
	sub	sp, sp, #4	
	stmfd	sp!, {r0}
	ldr	r0, L$_promIRQ    /*L$_promIRQ     */
	ldr	r0, [r0]
	str	r0, [sp, #4]    
	ldmfd	sp!, {r0, pc}

/*
;; ====================================================================
;; Name:	ROM_RESERVED
;; Function:	This routine helps to pass control to proper RESERVED
;;		handler once the RESERVED exception occurs
;; ====================================================================	
*/
_ARM_FUNCTION(romReserved)
_romReserved:
	sub	sp, sp, #4
	stmfd	sp!, {r0}
	ldr	r0, L$_promReserved         
	ldr	r0, [r0]
	str	r0, [sp, #4]        
	ldmfd	sp!, {r0, pc}
/*		
;; ====================================================================
;; Name:	ROM_DATAABORT
;; Function:	This routine helps to pass control to proper DATAABORT
;;		handler once the DATAABORT exception occurs
;; ====================================================================	
*/
_ARM_FUNCTION(romDataAbort)
_romDataAbort:
	sub	sp, sp, #4
	stmfd	sp!, {r0}
	ldr	r0, L$_promDataAbort   
	ldr	r0, [r0]
	str	r0, [sp, #4]
	ldmfd	sp!, {r0, pc}

/*
;; ====================================================================
;; Name:	ROM_PREFETCH
;; Function:	This routine helps to pass control to proper PREFETCH
;;		handler once the PREFETCH exception occurs
;; ====================================================================	
*/
_ARM_FUNCTION(romPrefetch)
_romPrefetch:
	sub	sp, sp, #4
	stmfd	sp!, {r0}
	ldr	r0, L$_promPrefetch    
	ldr	r0, [r0]          
	str	r0, [sp, #4]
	ldmfd	sp!, {r0, pc}

/*
;; ====================================================================
;; Name:	ROM_SWI
;; Function:	This routine helps to pass control to proper SWI handler
;;		once SWI is called by program
;; ====================================================================	
*/
_ARM_FUNCTION(romSwi)
_romSwi:
	sub	sp, sp, #4
	stmfd	sp!, {r0}
	ldr	r0, L$_promSwi     
	ldr	r0, [r0]
	str	r0, [sp, #4]
	ldmfd	sp!, {r0, pc}


/*	
;; ====================================================================
;; Name:	ROM_UNDEFINED
;; Function:	This routine helps to pass control to proper UNDEFINED
;;		handler once the UNDEFINED exception occurs
;; ====================================================================	
*/

_ARM_FUNCTION(romUndef)
_romUndef:
	sub	sp, sp, #4
	stmfd	sp!, {r0}
	ldr	r0, L$_promUndef               
	ldr	r0, [r0]            
	str	r0, [sp, #4]
	ldmfd	sp!, {r0, pc}
	

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor preforming substitution
 */

    .balign    4   


    
L$_HiPosn:
    .long    ROM_TEXT_ADRS + HiPosn - FUNC(romInit) 

L$_rStrtInRom:
    .long    ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L$_STACK_ADDR_ROM:
    .long    STACK_ADRS



  /* SDRAM System Initialization Data  */
L$_SystemInitDataSDRAM:
    .long    rBWSCON    
    .long    rROMCON0   
    .long    rROMCON1
    .long    rROMCON2
    .long    rROMCON3
    .long    rROMCON4
    .long    rROMCON5
    .long    rSDRAMCON6    
    .long    rSDRAMCON7
    .long    rREFCON    
    .long    rBANKSIZE
    .long    rMRSR6
    .long    rMRSR7



L$_promUndef:
    .long     S3C_EXC_BASE  /* undef handler */

L$_promSwi:
    .long     S3C_EXC_BASE + 0x04  /* swi handler */

L$_promPrefetch:
    .long     S3C_EXC_BASE + 0x08  

L$_promDataAbort:
    .long     S3C_EXC_BASE + 0x0c 

L$_promReserved:
    .long     S3C_EXC_BASE + 0x10

L$_promIRQ:
    .long     S3C_EXC_BASE + 0x14  /* IRQ */

L$_promFIQ:
    .long     S3C_EXC_BASE + 0x18