s3cboard.h

vxworks bsp,s3c2410的vxworks开发资料

#define rSDRAMCON6    ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))	


/* Bank 7(if SROM) parameter */
#define B7_Tacs		0x3	/* 4clk */
#define B7_Tcos		0x3	/* 4clk */
#define B7_Tacc		0x7	/* 14clk */
#define B7_Tcoh		0x3	/* 4clk */
#define B7_Tah		0x3	/* 4clk */
#define B7_Tacp		0x3	/* 6clk */
#define B7_PMC		0x0	/* normal(1data) */

/* Bank 7 parameter	 */
#define B7_MT		0x3	/* SDRAM */
#define B7_Trcd		0x0	/* 2clk */
#define B7_SCAN		0x0	/* 8bit */

#define rSDRAMCON7  ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))


/* REFRESH parameter */
#define REFEN		0x1	/* Refresh enable */
#define TREFMD		0x0	/* CBR(CAS before RAS)/Auto refresh  */
#define Trp			0x0	/* 2clk */
#define Trc			0x1	/* 5clk */
#define Tchr		0x2	/* 3clk */
/* REFCNT = 2048 + 1 - MCLK(MHz) * 15.6 64ms/4096=15.625us*64=1000 */
#define REFCNT		1113	/* period=15.6us, MCLK=60Mhz */
                        /* if PLLCLK change, this value has to be re-calculated */

#define rREFCON     ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)

#define rBANKSIZE   0x00 /* 0x10*/
#define rMRSR6      0x20
#define rMRSR7      0x20



/**************************************************************************
 * -> REFEXTCON : External I/O & Memory Refresh cycle Control Register 
 */

#define RefCycle          16         /*Unit [us], 1k refresh 16ms*/

/*RefCycle EQU 8 ;Unit [us], 1k refresh 16ms*/

#define CASSetupTime         0         /*0=1cycle, 1=2cycle*/
#define CASHoldTime          0         /*0=1cycle, 1=2cycle, 2=3cycle,
                                         3=4cycle, 4=5cycle,*/
#if (((2<<11)+1-(RefCycle*fMCLK)) < 0x3FF)
#define RefCycleValue     (((2<<11)+1-(RefCycle*fMCLK))<<21)
#else
#define RefCycleValue     (0x3FF<<21)
#endif

#define Tcsr              (CASSetupTime<<20) /* 1cycle */
#define Tcs               (CASHoldTime<<17)
#define ExtIOBase         0x183fd            /* Refresh enable, VSF=1*/

#define rREFEXTCON        (RefCycleValue+Tcsr+Tcs+ExtIOBase)

/******************************************************************
 *SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms
 */

#define SRefCycle          8         /*Unit [us], 4k refresh 64ms*/
#define ROWcycleTime       3         /*0=1cycle, 1=2cycle, 2=3cycle,
                                       3=4cycle, 4=5cycle,*/
#define SRefCycleValue     ((2048+1-(SRefCycle*fMCLK))<<21)
#define STrc               (ROWcycleTime<<17)
#define rSREFEXTCON        (SRefCycleValue+STrc+ExtIOBase)

/* interrupt levels */
#define INT_LVL_ADC        0    /* ADC Interrupt */
#define INT_LVL_RTC        1    /* Real Time Clock Interrupt */
#define INT_LVL_UTXD1      2    /* UART1 TX Interrupt */
#define INT_LVL_UTXD0      3    /* UART0 TX Interrupt */
#define INT_LVL_SIO        4    /* SIO Interrupt */
#define INT_LVL_IIC        5    /* I2C Interrupt */
#define INT_LVL_URXD1      6    /* UART 1 Rx Interrupt */
#define INT_LVL_URXD0      7    /* UART 0 Rx Interrupt */
#define INT_LVL_TIMER5     8    /* Timer 5 interrupt */
#define INT_LVL_TIMER4     9    /* Timer 4 interrupt */
#define INT_LVL_TIMER3     10    /* Timer 3 Interrupt */
#define INT_LVL_TIMER2     11    /* Timer 2 Interrupt  */
#define INT_LVL_TIMER1     12    /* Timer 1 interrupt */
#define INT_LVL_TIMER0     13    /* Timer 0 interrupt */
#define INT_LVL_UERR0_1    14    /* UERR0/1 interrupt */
#define INT_LVL_WDT        15    /* Watch dog interrupt */
#define INT_LVL_BDMA1      16    /* BDMA 1 Interrupt */
#define INT_LVL_BDMA0      17    /* BDMA 0 Interrupt */
#define INT_LVL_ZDMA1      18    /* ZDMA 1 Interrupt */
#define INT_LVL_ZDMA0      19    /* ZDMA 0 Interrupt */
#define INT_LVL_TICK       20    /* TICK Interrupt */
#define INT_LVL_EXTINT4567     21 /* External Interrup 4567 */
#define INT_LVL_EXTINT3        22 /* External Interrup 3 */
#define INT_LVL_EXTINT2        23 /* External Interrup 2 */
#define INT_LVL_EXTINT1        24 /* External Interrup 1 */
#define INT_LVL_EXTINT0        25 /* External Interrup 0 */
#define INT_LVL_GLOBAL         26

/* interrupt vectors */

#define INT_VEC_ADC          IVEC_TO_INUM(INT_LVL_ADC)    
#define INT_VEC_RTC          IVEC_TO_INUM(INT_LVL_RTC)    
#define INT_VEC_UTXD1        IVEC_TO_INUM(INT_LVL_UTXD1)  
#define INT_VEC_UTXD0        IVEC_TO_INUM(INT_LVL_UTXD0)  
#define INT_VEC_SIO          IVEC_TO_INUM(INT_LVL_SIO)    
#define INT_VEC_IIC          IVEC_TO_INUM(INT_LVL_IIC)    
#define INT_VEC_URXD1        IVEC_TO_INUM(INT_LVL_URXD1)  
#define INT_VEC_URXD0        IVEC_TO_INUM(INT_LVL_URXD0)  
#define INT_VEC_TIMER5       IVEC_TO_INUM(INT_LVL_TIMER5) 
#define INT_VEC_TIMER4       IVEC_TO_INUM(INT_LVL_TIMER4) 
#define INT_VEC_TIMER3       IVEC_TO_INUM(INT_LVL_TIMER3) 
#define INT_VEC_TIMER2       IVEC_TO_INUM(INT_LVL_TIMER2) 
#define INT_VEC_TIMER1       IVEC_TO_INUM(INT_LVL_TIMER1) 
#define INT_VEC_TIMER0       IVEC_TO_INUM(INT_LVL_TIMER0) 
#define INT_VEC_UERR0_1      IVEC_TO_INUM(INT_LVL_UERR0_1)
#define INT_VEC_WDT          IVEC_TO_INUM(INT_LVL_WDT)    
#define INT_VEC_BDMA1        IVEC_TO_INUM(INT_LVL_BDMA1)  
#define INT_VEC_BDMA0        IVEC_TO_INUM(INT_LVL_BDMA0)  
#define INT_VEC_ZDMA1        IVEC_TO_INUM(INT_LVL_ZDMA1)  
#define INT_VEC_ZDMA0        IVEC_TO_INUM(INT_LVL_ZDMA0)  
#define INT_VEC_TICK         IVEC_TO_INUM(INT_LVL_TICK)   
#define INT_VEC_EXTINT4567   IVEC_TO_INUM(INT_LVL_EXTINT4567)
#define INT_VEC_EXTINT3      IVEC_TO_INUM(INT_LVL_EXTINT3)
#define INT_VEC_EXTINT2      IVEC_TO_INUM(INT_LVL_EXTINT2)
#define INT_VEC_EXTINT1      IVEC_TO_INUM(INT_LVL_EXTINT1)
#define INT_VEC_EXTINT0      IVEC_TO_INUM(INT_LVL_EXTINT0)


/**********************************************************************************************************
 * Cache Definitions
 *
 */

#define S3C44B_NON_CACHE_0_START    0x0000
#define S3C44B_NON_CACHE_0_END      0xc000

#define S3C44B_STALL_DISABLE    (0)
#define S3C44B_CACHE_DISABLE   ( 0x0 << 1 )
#define S3C44B_CACHE_4K        ( 0x1 << 1 )
#define S3C44B_CACHE_8K        ( 0x3 << 1 )
#define S3C44B_CACHE_MODE      ( 0x3 << 1 )
#define S3C44B_WRITE_BUFF      ( 0x1 << 3 )
#define S3C44B_CACHE_ENABLE    S3C44B_CACHE_MODE
#define S3C44B_TAGRAM          0x10002000
#define S3C44B_LRU             0x10004000


/*
 *
 * definitions for the SBCARM7 Timer:
 * two timers clocked from same source and with the same reload overhead
 */
#define SBCARM7_TIMER_SYS_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_SYS_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_AUX_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_AUX_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)

#define SYS_TIMER_CLK               (S3C44B_CPU_SPEED)    /* Frequency of counter/timer */
#define AUX_TIMER_CLK               (S3C44B_CPU_SPEED)    /* Frequency of counter/timer */

#if 0
#define SBCARM7_RELOAD_TICKS            3        /* three ticks to reload timer */

#define SYS_TIMER_CLEAR(x)          (SBCARM7_TIMER_T1CLEAR(x))    /* sys Clk is timer 1  */
#define SYS_TIMER_CTRL(x)           (SBCARM7_TIMER_T1CTRL(x))
#define SYS_TIMER_LOAD(x)           (SBCARM7_TIMER_T1LOAD(x))
#define SYS_TIMER_VALUE(x)          (SBCARM7_TIMER_T1VALUE(x))
#define SBCARM7_TIMER_VALUE_MASK        0xFFFF
#define AUX_TIMER_CLEAR(x)          (SBCARM7_TIMER_T2CLEAR(x))    /* aux Clk is timer 2  */
#define AUX_TIMER_CTRL(x)           (SBCARM7_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x)           (SBCARM7_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x)          (SBCARM7_TIMER_T2VALUE(x))
#endif

#define SYS_TIMER_INT_LVL           (INT_LVL_TIMER5) /*(INT_LVL_TIMER0)*/
#define AUX_TIMER_INT_LVL           (INT_LVL_TIMER4) /* (INT_LVL_TIMER1) */

/******************************************************************************************
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * Note that it takes 3 ticks to reload the 16-bit counter and we don't
 * accept values that would mean a zero reload value as we don't know what
 * that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value+3))
 * max frequency = rounddown(clock_rate/(min_counter_value+3))
 * i.e.              SYS_CLK_RATE_MAX (SYS_TIMER_CLK/4)
 * However, we must set maxima that are sustainable on a running
 * system. Experiments suggest that a 16MHz PID board can sustain a
 * maximum clock rate of 10000 to 10500. The values below have been
 * chosen so that there is a reasonable margin and the BSP passes the
 * test suite.
 */

#define SYS_CLK_RATE_MIN      10
#define SYS_CLK_RATE_MAX      10000
#define AUX_CLK_RATE_MIN      2
#define AUX_CLK_RATE_MAX      10000

/*
 * Our MAC address definition.  User can change this value as
 * per requirement.  Note, the least significant byte of the
 * address is changed to the value of the user DIP switch setting.
 * SW4-D0 is the least significant bit of this byte.  Open=0.
 */

#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }

/* register read macros */
/* 32bit read word */
#ifndef S3C44B_REG_READW
#define S3C44B_REG_READW(reg, result) \
    ((result) = *((volatile UINT32 *)(reg)))
#endif /* S3C44B_REG_READW */

/* 16bit read half-word */
#ifndef S3C44B_REG_READH
#define S3C44B_REG_READH(reg, result) \
    ((result) = *((volatile UINT16 *)(reg)))
#endif /* S3C44B_REG_READH */

/* 8bit read byte */ /* for ADC,RTC,UART regs */
#ifndef S3C44B_REG_READB
#define S3C44B_REG_READB(reg, result) \
    ((result) = *((volatile UINT8 *)(reg)))
#endif /* S3C44B_REG_READB */

/* register write macros*/
#ifndef S3C44B_REG_WRITEW
#define S3C44B_REG_WRITEW(reg, data) \
    (*((volatile UINT32 *)(reg)) = (data))
#endif /*S3C44B_REG_WRITEW*/

#ifndef S3C44B_REG_WRITEH
#define S3C44B_REG_WRITEH(reg, data) \
    (*((volatile UINT16 *)(reg)) = (data))
#endif /*S3C44B_REG_WRITEH*/

#ifndef S3C44B_REG_WRITEB
#define S3C44B_REG_WRITEB(reg, data) \
    (*((volatile UINT8 *)(reg)) = (data))
#endif /* S3C44B_REG_WRITEB */


#ifdef __cplusplus
}
#endif

#endif    /* __INCs3cboard */