s3cboard.h

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/* s3cBoard.h - S3C44B0X ARM7 Board header file */


/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
This file contains I/O address and related constants for the S3C44B0X ARM7 board.
*/

#ifndef    __INCs3cboard
#define    __INCs3cboard

#ifdef __cplusplus
extern "C" {
#endif

#include "s3c44b.h"


/* #define TARGET_SBCARM7*/


#define SBCARM7_FLASH_BASE 0x1000000

/* exception base */
#define S3C_EXC_BASE         0x0c000100

/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS  0x0C000000    /* 0x00000000    fixed */
#define LOCAL_MEM_BUS_ADRS    0x0C000000    /* fixed */


#define BUS                   BUS_TYPE_NONE


#define S3C44B_CPU_SPEED         64000000    /* CPU clocked at 60 MHz. The timer */
                    /* speed is related to this */
                    /* PLL CLK jhf 02-18 */


/* definitions for the KS32C50100 UART */

#define N_S3C44B_UART_CHANNELS     2        /* number of  UART chans */
#define N_SIO_CHANNELS          N_S3C44B_UART_CHANNELS
#define N_UART_CHANNELS         N_S3C44B_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart */


/* LED Registers (write) */




/****************************************************************************
 *
 * Format of the Program Status Register 
 */

#define FBit         0x40
#define IBit         0x80
#define LOCKOUT      0xC0     /* Interrupt lockout value */
#define LOCK_MSK     0xC0     /* Interrupt lockout mask value */
#define MODE_MASK    0x1F     /* Processor Mode Mask */
#define UDF_MODE     0x1B     /* Undefine Mode(UDF) */
#define ABT_MODE     0x17     /* Abort Mode(ABT) */
#define SUP_MODE     0x13     /* Supervisor Mode (SVC) */
#define IRQ_MODE     0x12     /* Interrupt Mode (IRQ) */
#define FIQ_MODE     0x11     /* Fast Interrupt Mode (FIQ) */
#define USR_MODE     0x10     /* User Mode(USR) */

/*************************************************************************
 * SYSTEM CLOCK 
 */

#define MHz            1000000
#define fMCLK_MHz      50000000     /* 50MHz, KS32C50100*/
#define fMCLK          50           /* fMCLK_MHz/MHz */

/*************************************************************************
 * SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
 */

/* SYSCFG Register Value */
#define SYSCONFIG_VAL           0x07ffffa0    /* System Configuration Value, EDO RAM */
#define SYSCONFIG_VAL_SDRAM     0x87ffffa0    /* System Configuration Value, SDRAM */

/* CLKCON Clock configuration register Values */
#define tCDIV           (0<<0)
#define tWE             (0<<16)
#define tMUX            (0<<17)
#define tAC             (0<<18)
#define tTEST           (0<<31)


#define rCLKCON         (tCDIV+tWE+tMUX+tAC+tTEST)

/* EXTACONx External I/O access timing register Values */
#define tCOS0           (1<<0)
#define tACS0           (1<<3)
#define tCOH0           (1<<6)
#define tACC0           (1<<9)
#define tCOS1           (1<<16)
#define tACS1           (1<<19)
#define tCOH1           (1<<22)
#define tACC1           (1<<25)

#define rEXTACON0       (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)

#define tCOS2           (7<<0)
#define tACS2           (7<<3)
#define tCOH2           (7<<6)
#define tACC2           (7<<9)
#define tCOS3           (7<<16)
#define tACS3           (7<<19)
#define tCOH3           (7<<22)
#define tACC3           (7<<25)

#define rEXTACON1       (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)

/***********************************************************
 *
 * BWSCON : Bus Width and Wait Control register
 */
#define BW_ENDIAN    (0<<0) /* bank 0 endian ,read only,NOR flash */
#define BW_DW0       (0<<1) /* bank 0 bus width,read only, should be 01 */

#define BW_DW1       (0<<4) /* bank 1 00=8bit NAND Flash */
#define BW_WS1       (0<<6) /* bank 1 wait =disable */
#define BW_ST1       (0<<7) /* Not using UB/LB */

#define BW_DW2       (0<<8) /* bank 2 8bit PDIUSBD12 */
#define BW_WS2       (0<<10) /* bank 2 wait = disable */
#define BW_ST2       (0<<11) /* Not using UB/LB */

#define BW_DW3       (1<<12) /* bank3 16bit RTL8019 */
#define BW_WS3       (0<<14)
#define BW_ST3       (0<<15)

#define BW_DW4       (1<<16) /* bank4 16bit Not Used */
#define BW_WS4       (0<<18)
#define BW_ST4       (0<<19)

#define BW_DW5       (1<<20) /* bank5 16bit Not Used */
#define BW_WS5       (0<<22)
#define BW_ST5       (0<<23)

#define BW_DW6       (1<<24) /* bank6 16bit SDRAM  */
#define BW_WS6       (0<<26)
#define BW_ST6       (0<<27)

#define BW_DW7       (1<<28) /* bank7 16bit SDRAM */
#define BW_WS7       (0<<30)
#define BW_ST7       (0<<31)

#define rBWSCON      ( BW_ENDIAN+BW_DW0    + \
                      BW_DW1+BW_WS1+BW_ST1 + \
                      BW_DW2+BW_WS2+BW_ST2 + \
                      BW_DW3+BW_WS3+BW_ST3 + \
                      BW_DW4+BW_WS4+BW_ST4 + \
                      BW_DW5+BW_WS5+BW_ST5 + \
                      BW_DW6+BW_WS6+BW_ST6 + \
                      BW_DW7+BW_WS7+BW_ST7 )

/* MEMORY CONTROL PARAMETERS */


/* Bank 0 parameter */
#define B0_Tacs		0x0	/* 0clk */
#define B0_Tcos		0x0	/* 0clk */
#define B0_Tacc		0x6	/* 10clk */
#define B0_Tcoh		0x0	/* 0clk */
#define B0_Tah		0x0	/* 0clk */
#define B0_Tacp		0x0	/* 0clk */
#define B0_PMC		0x0	/* normal(1data) */

/* ROMCON0 : ROM Bank0 Control register */
#define rROMCON0   ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))

/* Bank 1 parameter */
#define B1_Tacs		0x3	/* 4clk */
#define B1_Tcos		0x3	/* 4clk */
#define B1_Tacc		0x7	/* 14clk */
#define B1_Tcoh		0x3	/* 4clk */
#define B1_Tah		0x3	/* 4clk */
#define B1_Tacp		0x3	/* 6clk */
#define B1_PMC		0x0	/* normal(1data) */

/* ROMCON1 : ROM Bank1 Control register */
#define rROMCON1    ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))

/* Bank 2 parameter */
#define B2_Tacs		0x3	/* 4clk */
#define B2_Tcos		0x3	/* 4clk */
#define B2_Tacc		0x7	/* 14clk */
#define B2_Tcoh		0x3	/* 4clk */
#define B2_Tah		0x3	/* 4clk */
#define B2_Tacp		0x3	/* 6clk */
#define B2_PMC		0x0	/* normal(1data) */

/* ROMCON2 : ROM Bank2 Control register */
#define rROMCON2    ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))

/* Bank 3 parameter */
#define B3_Tacs		0x3	/* 4clk */
#define B3_Tcos		0x3	/* 4clk */
#define B3_Tacc		0x7	/* 14clk */
#define B3_Tcoh		0x3	/* 4clk */
#define B3_Tah		0x3	/* 4clk */
#define B3_Tacp		0x3	/* 6clk */
#define B3_PMC		0x0	/* normal(1data) */

#define rROMCON3    ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))

/* Bank 4 parameter */
#define B4_Tacs		0x3	/* 4clk */
#define B4_Tcos		0x3	/* 4clk */
#define B4_Tacc		0x7	/* 14clk*/
#define B4_Tcoh		0x3	/* 4clk */
#define B4_Tah		0x3	/* 4clk */
#define B4_Tacp		0x3	/* 6clk */
#define B4_PMC		0x0	/* normal(1data) */

#define rROMCON4    ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))

/* Bank 5 parameter */
#define B5_Tacs		0x3	/* 4clk */
#define B5_Tcos		0x3	/* 4clk */
#define B5_Tacc		0x7	/* 14clk */
#define B5_Tcoh		0x3	/* 4clk */
#define B5_Tah		0x3	/* 4clk */
#define B5_Tacp		0x3 /* 6clk */
#define B5_PMC		0x0	/* normal(1data) */

#define rROMCON5    ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))

/* Bank 6(if SROM) parameter */
#define B6_Tacs		0x3	/* 4clk */
#define B6_Tcos		0x3	/* 4clk */
#define B6_Tacc		0x7	/* 14clk */
#define B6_Tcoh		0x3	/* 4clk */
#define B6_Tah		0x3	/* 4clk */
#define B6_Tacp		0x3	/* 6clk */
#define B6_PMC		0x0/* normal(1data) */

/* Bank 6 parameter SDRAM */	
#define B6_MT		0x3	/* SDRAM */
#define B6_Trcd		0x0	/* 2clk */
#define B6_SCAN		0x0	/* 8bit */