s3c44b.h

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/* s3c44b.h - header for Samsung ks32c with ARM7 core */

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,12apr01,m_h  created from snds100 template.
*/

#ifndef __INCs3c44b
#define __INCs3c44b

#ifdef __cplusplus
extern "C" {
#endif

/*************************************************************************
* S3C44B0X  REGISTERS DEFINITION
*
*/

/*----------------------------------------*/
/* system configure register */

#define S3C44B_SYSCFG          0x01c00000
#define S3C44B_NCACH_BE0       0x01c00004
#define S3C44B_NCACH_BE1       0x01c00008

/* Macro definition with SYSCFG */
#define S3C44B_SYS_SE          0x1                /* enable stall */
#define S3C44B_SYS_FULLCACHE   0x6                /* full cache 0x3<<1 */
#define S3C44B_SYS_HALFCACHE   0x2                /* half cache half sram */
#define S3C44B_SYS_NOCAHE      0x0                /* all sram */
#define S3C44B_SYS_WBUF        0x8                /* write buffer enable */
#define S3C44B_SYS_RSE         0x10               /* enable read stall */
#define S3C44B_SYS_DA          0x20               /* enable data abort */

/*----------------------------------------*/
/* INTERRUPT */
#define S3C44B_INTCON          (0x01e00000)       /* interrupt controller registers */
#define S3C44B_INTPND          (0x01e00004)       /* interrupt pending register */
#define S3C44B_INTMOD          (0x01e00008)       /* interrupt mode register */
#define S3C44B_INTMASK		   (0x01e0000c)       /* interrupt mask register */
#define S3C44B_FIQ_ENABLE      (~(1 << 0))        /* 0 = FIQ interrupt enable (
                                                  Not allowed vectored interrupt mode)*/
#define S3C44B_IRQ_ENABLE      (0 << 1)           /* 0 = IRQ interrupt enable*/
#define S3C44B_IRQ_MODE        (1 << 2)            /* 1 = Non-vectored interrupt mode */
#define S3C44B_FIQ_DISABLE     (1 << 0)
/* vector interrupt register */
#define S3C44B_I_PSLV          (0x01e00010)       /* R/W IRQ priority of slave register */
#define S3C44B_I_PMST          (0x01e00014)       /* R/W IRQ priority of master register */ 
#define S3C44B_I_CSLV          (0x01e00018)       /* R Current IRQ priority of slave register */
#define S3C44B_I_CMST          (0x01e0001c)       /* R Current IRQ priority of master register */
#define S3C44B_I_ISPR          (0x01e00020)       /* R IRQ interrupt service pending register
                                                  (Only one service bit can be set)*/



#define S3C44B_I_ISPC          (0x01e00024)       /* W IRQ interrupt service pending clear register */
#define S3C44B_F_ISPC          (0x01e0003c)       /* FIQ interrupt service pending clear register */

#define S3C44B_INTENB           S3C44B_INTMASK

#define S3C44B_INTNUMS          26
#define S3C44B_INTMASK_VAL      0x03ffffff /* 0x07ffffff*/
#define S3C44B_INTPND_VAL       0x03ffffff
#define S3C44B_INTMOD_IRQ       0x0000


 /* I/O Port Interface  */


/* IIC Registers */

/* definitions for the KS32C50100 UART */
#define SERIAL_A_BASE_ADR           0x01d00000     /* UART 0 base address */
#define SERIAL_B_BASE_ADR           0x01d04000     /* UART 1 base address */


/* watch dog */
#define S3C44B_WTCON	            0x01d30000

/* I/O port */
#define S3C44B_PCONA                0x01d20000
#define S3C44B_PDATA                0x01d20004

#define S3C44B_PCONB                0x01d20008
#define S3C44B_PDATB                0x01d2000c

#define S3C44B_PCONC                0x01d20010
#define S3C44B_PDATC                0x01d20014
#define S3C44B_PUPC		            0x01d20018

#define S3C44B_PCOND                0x01d2001c
#define S3C44B_PDATD                0x01d20020
#define S3C44B_PUPD		            0x01d20024

/* PortE for Led ctrl */
#define S3C44B_PCONE                0x01d20028
#define S3C44B_PDATE                0x01d2002c
#define S3C44B_PUPE                 0x01d20030


#define S3C44B_PCONF                0x01d20034
#define S3C44B_PDATF                0x01d20038
#define S3C44B_PUPF		            0x01d2003c

#define S3C44B_PCONG                0x01d20040
#define S3C44B_PDATG                0x01d20044
#define S3C44B_PUPG		            0x01d20048

#define S3C44B_SPUCR		        0x01d2004c
#define S3C44B_EXTINT               0x01d20050
#define S3C44B_EXTINPND             0x01d20054

/* real time controller  */
#ifdef _S3C44B_BIG_ENIDAN
#define S3C44B_RTCCON	            0x01d70043
#define S3C44B_RTCALM               0x01d70053
#define S3C44B_ALMSEC               0x01d70057
#define S3C44B_ALMMIN               0x01d7005b
#define S3C44B_ALMHOUR              0x01d7005f
#define S3C44B_ALMDAY               0x01d70063
#define S3C44B_ALMMON               0x01d70067
#define S3C44B_ALMYEAR              0x01d7006b
#define S3C44B_RTCRST               0x01d7006f
#define S3C44B_BCDSEC               0x01d70073
#define S3C44B_BCDMIN               0x01d70077
#define S3C44B_BCDHOUR              0x01d7007b
#define S3C44B_BCDDAY               0x01d7007f
#define S3C44B_BCDDATE              0x01d70083
#define S3C44B_BCDMON               0x01d70087
#define S3C44B_BCDYEAR              0x01d7008b
#define S3C44B_TICINT               0x01d7008e
#else
#define S3C44B_RTCCON               0x01d70040
#define S3C44B_RTCALM               0x01d70050
#define S3C44B_ALMSEC               0x01d70054
#define S3C44B_ALMMIN               0x01d70058
#define S3C44B_ALMHOUR              0x01d7005c
#define S3C44B_ALMDAY               0x01d70060
#define S3C44B_ALMMON               0x01d70064
#define S3C44B_ALMYEAR              0x01d70068
#define S3C44B_RTCRST               0x01d7006c
#define S3C44B_BCDSEC               0x01d70070
#define S3C44B_BCDMIN               0x01d70074
#define S3C44B_BCDHOUR              0x01d70078
#define S3C44B_BCDDAY               0x01d7007c
#define S3C44B_BCDDATE              0x01d70080
#define S3C44B_BCDMON               0x01d70084
#define S3C44B_BCDYEAR              0x01d70088
#define S3C44B_TICINT               0x01d7008c
#endif

/* Clock Controller */
#define S3C44B_PLLCON	            0x01d80000
#define S3C44B_CLKCON	            0x01d80004
#define S3C44B_CLKSLOW              0x01d80008
#define S3C44B_LOCKTIME             0x01d8000c

/* BDMA registers */
#define S3C44B_BDCON0               0x01f80000


#define S3C44B_BDISRC0              0x01f80004
#define S3C44B_BDIDES0              0x01f80008
#define S3C44B_BDICNT0              0x01f8000c

#define S3C44B_BDCON1               0x01f80020
#define S3C44B_BDISRC1              0x01f80024
#define S3C44B_BDIDES1              0x01f80028
#define S3C44B_BDICNT1              0x01f8002c


/* MCLK macros */
/*
Fout = (M_DIV+8)*Fin/((P_DIV+2)*2^S_DIV)
PLL Guide
Fout*2^S_DIV < 170Mhz
S_DIV should be as great as possible
1Mhz < Fin/(P_DIV+2) < 2Mhz
Fout > 20Mhz
*/
#define PLLCLK    64000000

#if PLLCLK == 24000000
    #define M_DIV	0x34
    #define P_DIV   0x3
    #define S_DIV   0x2
#endif

#if PLLCLK == 32000000	
    #define M_DIV	0x48	/* Fin=8MHz Fout=32MHz */
    #define P_DIV	0x3
    #define S_DIV	0x2	
#endif

#if PLLCLK == 40000000	
    #define M_DIV	0x5c	/* Fin=8MHz Fout=40MHz */
    #define P_DIV	0x3
    #define S_DIV	0x2
#endif

#if	PLLCLK == 48000000	
    #define M_DIV	0x34	/* Fin=8MHz Fout=48MHz */
    #define P_DIV	0x3
    #define S_DIV	0x1		
#endif

#if PLLCLK == 60000000	
    #define M_DIV	0x43	/* Fin=8MHz Fout=60MHz */
    #define P_DIV	0x3
    #define S_DIV	0x1		
#endif

#if PLLCLK == 64000000	
#if 0
    #define M_DIV	0x48	/* Fin=8MHz Fout=64MHz */
    #define P_DIV	0x3
    #define S_DIV	0x1		
#endif
    #define M_DIV	0x38	/* Fin=8MHz Fout=64MHz */
    #define P_DIV	0x2
    #define S_DIV	0x1		

#endif	

#if PLLCLK == 66000000	
    #define M_DIV	0x5b	/* Fin=8MHz Fout=66MHz */
    #define P_DIV	0x4
    #define S_DIV	0x1		
#endif

#ifdef __cplusplus
}
#endif

#endif /* __INCs3c44b */