📄 s3c44bsio.h
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/* s3c44bSio.h - header file for Samsung S3C44B0X serial driver *//* Copyright 1984-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01c,16jul02,m_h C++ protection01b,26apr01,m_h convert tabs to spaces for readability01a,12apr01,m_h created from snds100 template.*/#ifndef __INCs3c44bSio#define __INCs3c44bSio#ifdef __cplusplusextern "C" {#endif#include "sioLib.h"#include "s3c44b.h"/* UART Register offsets from Base Address */#define S3C44B_ULCON 0x0000 /* UART Line Control Registers */#define S3C44B_UCON 0x0004 /* UART Control Register */#define S3C44B_FCON 0x0008 /* FIFO control register */#define S3C44B_MCON 0x000C /* Modem control register */#define S3C44B_UTRSTAT 0x0010 /* UART Tx/Rx Status Register */#define S3C44B_UERSTAT 0x0014 /* UART error status register */#define S3C44B_UFSTAT 0x0018 /* UART FIFO status register */#define S3C44B_UMSTAT 0x001C /* UART modem status register */#ifdef _S3C44B_BIG_ENIDAN#define S3C44B_UTXBUF 0x0023 /*UART Transmit Buffer Register*/#define S3C44B_URXBUF 0x0027 /*UART Receive Buffer Register*/#else#define S3C44B_UTXBUF 0x0020 /*UART Transmit Buffer Register*/#define S3C44B_URXBUF 0x0024 /*UART Receive Buffer Register*/#endif#define S3C44B_UBRDIV 0x0028 /*UART Baud Rate Divisor Register*//* Bit definitions within ULCON0/1 Line Control Register*/#define WORD_LEN 0x03 /* Set Word Length=8 0x00= 5bits 0x01= 6bits 0x02= 7bits 0x03= 8bits */#define ONE_STOP 0x00 /* One Stop Bit 0x00= 1 stop bit 0x04= 2 stop bits*/#define PARITY_NONE 0x00 /* Set No Parity B'000000 */#define PARITY_ODD 0x20 /* Set Odd Parity B'100000 */#define PARITY_EVEN 0x28 /* Set Even Parity B'101000 */#define PARTIY_F_1 0x30 /* set parity force 1 B'110000 */#define PARITY_F_0 0x38 /* set parity force 0 B'111000 */#define NORMAL_MODE 0x00 /* normal mode */#define IR_MODE 0x40 /* Infra-Red Tx/Rx Mode B'01000000 *//* Bit definitions within UCON0/1 Control Register*/#define UCON_RX 0x01 /* Receive Mode -Interrupt 0x00= disalbe,0x01= interrup or polling 0x02= BDMA0 request(only for UART0) 0x03= BDMA1 request(only for UART1) */#define UCON_TX 0x04 /* Transmit Mode-Interrupt 0x00= disable, 0x04= interrup or polling 0x08= BDMA0(for UART0) 0x0C= BDMA1(for UART1) */#define UCON_BREAK 0x00 /* Send Break 0x00= normal 0x10= send break signal */#define UCON_LOOPBACK 0x00 /* loop back mode mode 0x000= normal operation 0x20= loop back */#define UCON_RXSTAT_EN 0x40 /* Rx error Status Interrrupt -Enable 0x00= disable 0x40= enable */#define UCON_RXTIMOUT_EN 0x80 /* enable Rx time out interrupt when FIFO is enabled. The interrupt is a receive interrup 0x0= Disable 0x80= Enable */#define UCON_RXINT_TYPE 0x000 /* Interrupt request type 0x000= Pulse(interrupt is requested the instant Rx buffer receivers the data) 0x100= Level(Interrupt is requested while Rx buffer is receiving the data) */ #define UCON_TXINT_TYPE 0x200 /* Tx interrupt request type 0x000= Pulse(Interrupt is requested the instant Tx buffer becomes empty) 0x200= Level(interrupt is requested while Tx buffer is empty) */ #define UCON_RX_TX_RESET 0xFF0 /* Rx and Tx Reset *//* Bit definitions within USTAT0/1 Status Register*/#define USTAT_RX_READY 0x01 /* this bit automatically set to 1 when the receive buffer register contains valid data, received over the RxDn port 0= Completely empy 1= The buffer register has a received data Note: If the UART uses the FIFO, users should check Rx FIFO Count bits in the UFSTAT register instead of this bit*/#define USTAT_TX_READY 0x02 /* 0= The buffer register is not empty 1= Empty */ #define USTAT_TXSHT_EMPTY 0x04 /* 0= Not Empty 1= Transmit hold & shifter register empty */ /* Bit definitions in UART Status register */ #define USTAT_OVERRUN_ERR 0x01 /* Over Run Error*/#define USTAT_PARITY_ERR 0x02 /* Parity Error*/#define USTAT_FRAME_ERR 0x04 /* Frame Error*/ #define USTAT_BREAK_DETECT 0x08 /* This bit is automatically set to 1 to indicate that a break signal has been received. 0 = No break receive 1 = Break receive */ /* UART Baud Rate Divisor Time Constant Value (MCLK = 64MHz) */#define S3C44B_BRDV_1200 (3125 - 1) /* Baud_Rate 1200*/#define S3C44B_BRDV_2400 (1563 - 1) /* Baud_Rate 2400*/#define S3C44B_BRDV_4800 (781 - 1) /* Baud_Rate 4800*/#define S3C44B_BRDV_9600 (391 - 1) /* Baud_Rate 9600*/#define S3C44B_BRDV_19200 (195 - 1) /* Baud_Rate 19200*/#define S3C44B_BRDV_38400 (104 - 1) /* Baud_Rate 38400*/#define S3C44B_BRDV_57600 (65 - 1) /* Baud_Rate 57600*/#define S3C44B_BRDV_115200 (35 - 1) /* Baud_Rate 115200*//* device and channel structures */typedef struct { /* must be first */ SIO_CHAN sio; /* standard SIO_CHAN element */ /* callbacks */ STATUS (*getTxChar) (void *, char*); void (*putRcvChar) (void *, char ); void * getTxArg; void * putRcvArg; /* register addresses */ UINT32 * regs; /*UART Registers*/ /* interrupts */ UINT8 intLevelRx; /* recv interrupt Level for this device*/ UINT8 intLevelTx; /* transmit interrupt Level for this device*/ /* misc */ UINT32 regDelta; /* register address spacing */ uint_t options; /* Hardware options */ int mode; /* current mode (interrupt or poll) */ int baudRate; /* input clock frequency */ } S3C44B_CHAN;/* function prototypes */#if defined(__STDC__)extern void s3c44bDevInit (S3C44B_CHAN *pChan); extern void s3c44bDevInit2 (S3C44B_CHAN *pChan); extern void s3c44bIntRcv (S3C44B_CHAN *pChan);extern void s3c44bIntTx (S3C44B_CHAN *pChan);#else /* __STDC__ */extern void s3c44bDevInit ();extern void s3c44bDevInit2 ();extern void s3c44bIntRcv ();extern void s3c44bIntTx ();#endif /* __STDC__ */#ifdef __cplusplus}#endif#endif /* __INCs3c44bSio */⌨️ 快捷键说明
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