d11.h

wi-fi sources for asus wl138g v2 pci card

#define	SKL_INDEX_SHIFT		4
#define	SKL_ALGO_MASK		0x07
#define	SKL_ALGO_SHIFT		0

#define	WSEC_MODE_OFF		0
#define	WSEC_MODE_HW		1
#define	WSEC_MODE_SW		2

#define	WSEC_ALGO_OFF		0
#define	WSEC_ALGO_WEP1		1
#define	WSEC_ALGO_TKIP		2
#define	WSEC_ALGO_AES		3
#define	WSEC_ALGO_WEP128	4
#define	WSEC_ALGO_AES_LEGACY	5
#define	WSEC_ALGO_NALG		6

#define	AES_MODE_NONE		0
#define	AES_MODE_CCM		1
#define	AES_MODE_OCB_MSDU	2
#define	AES_MODE_OCB_MPDU	3

/* WEP_CTL (Rev 0) */
#define	WECR0_KEYREG_SHIFT	0
#define	WECR0_KEYREG_MASK	0x7
#define	WECR0_DECRYPT		(1 << 3)
#define	WECR0_IVINLINE		(1 << 4)
#define	WECR0_WEPALG_SHIFT	5
#define	WECR0_WEPALG_MASK	(0x7 << 5)
#define	WECR0_WKEYSEL_SHIFT	8
#define	WECR0_WKEYSEL_MASK	(0x7 << 8)
#define	WECR0_WKEYSTART		(1 << 11)
#define	WECR0_WEPINIT		(1 << 14)
#define	WECR0_ICVERR		(1 << 15)

/* Frame template map byte offsets */
#define	T_ACTS_TPL_BASE		(0)
#define	T_NULL_TPL_BASE		(0xc * 2)
#define	T_QNULL_TPL_BASE	(0x1c * 2)
#define	T_RR_TPL_BASE		(0x2c * 2)
#define	T_BCN0_TPL_BASE		(0x34 * 2)
#define	T_PRS_TPL_BASE		(0x134 * 2)
#define	T_BCN1_TPL_BASE		(0x234 * 2)


#define T_RAM_ACCESS_SZ		4	/* template ram is 4 byte access only */

/* Shared Mem byte offsets */

/* Location where the ucode expects the corerev */
#define	M_MACHW_VER		(0x00b * 2)

/* WME shared memory */
#define M_EDCF_STATUS_OFF	(0x007 * 2)
#define M_TXF_CUR_INDEX		(0x018 * 2)
#define M_EDCF_QINFO		(0x120 * 2)

/* PS-mode related parameters */
#define	M_DOT11_SLOT		(0x008 * 2)
#define	M_DOT11_DTIMPERIOD	(0x009 * 2)
#define	M_NOSLPZNATDTIM		(0x026 * 2)

/* Beacon-related parameters */
#define	M_BCN0_FRM_BYTESZ	(0x00c * 2)	/* Bcn 0 template length */
#define	M_BCN1_FRM_BYTESZ	(0x00d * 2)	/* Bcn 1 template length */
#define	M_BCN_TXTSF_OFFSET	(0x00e * 2)
#define	M_TIMBPOS_INBEACON	(0x00f * 2)
#define	M_SFRMTXCNTFBRTHSD	(0x022 * 2)
#define	M_LFRMTXCNTFBRTHSD	(0x023 * 2)
#define	M_BCN_PCTLWD		(0x02a * 2)

/* ACK/CTS related params */
#define	M_RSP_PCTLWD		(0x011 * 2)


/* Rx-related paramenters */
#define	M_RX_PAD_DATA_OFFSET	(0x01a * 2)

/* WEP Shared mem data */
#define	M_SEC_DEFIVLOC		(0x01e * 2)
#define	M_SEC_VALNUMSOFTMCHTA	(0x01f * 2)
#define	M_PHYVER		(0x028 * 2)
#define	M_PHYTYPE		(0x029 * 2)
#define	M_SECRXKEYS_PTR		(0x02b * 2)
#define	M_SECKINDXALGO_BLK	(0x2ea * 2)
#define	M_SECPSMRXTAMCH_BLK	(0x2fa * 2)
#define	M_TKIP_TSC_TTAK		(0x18c * 2)
#define	D11_MAX_KEY_SIZE	16

#define	M_MAX_ANTCNT		(0x02e * 2)	/* antenna swap threshold */

/* Probe response related parameters */
#define	M_SSIDLEN		(0x024 * 2)
#define	M_PRB_RESP_FRM_LEN	(0x025 * 2)
#define	M_PRS_MAXTIME		(0x03a * 2)
#define	M_SSID			(0xb0 * 2)
#define	M_CTXPRS_BLK		(0xc0 * 2)
#define	C_CTX_PCTLWD_POS	(4 * 2)



/* Host flags to turn on ucode options */
#define	M_HOST_FLAGS		(0x02f * 2)
#define	M_HOST_FLAGS2		(0x030 * 2)
#define	M_HOST_FLAGS_SZ		16

#define M_RADAR_REG		(0x033 * 2)


#define	M_RF_RX_SP_REG1		(0x036 * 2)


/* Background noise measure */
#define	M_JSSI_0		(0x44 * 2)
#define	M_JSSI_1		(0x45 * 2)
#define	M_JSSI_AUX		(0x46 * 2)

/* TX fifo sizes */
#define M_FIFOSIZE0		(0x4c * 2)
#define M_FIFOSIZE1		(0x4d * 2)
#define M_FIFOSIZE2		(0x4e * 2)
#define M_FIFOSIZE3		(0x4f * 2)
#define D11_MAX_TX_FRMS		32		/* max frames allowed in tx fifo */

#define M_CURCHANNEL		(0x50 * 2)
#define M_CURCHANNEL_5G		0x0100;
#define M_CURCHANNEL_MAX	0x00FF;

/* last posted frameid on the bcmc fifo */
#define M_BCMC_FID		(0x54 * 2)
#define INVALIDFID		0xffff

/* Rate table offsets */
#define	M_RT_DIRMAP_A		(0xe0 * 2)
#define	M_RT_BBRSMAP_A		(0xf0 * 2)
#define	M_RT_DIRMAP_B		(0x100 * 2)
#define	M_RT_BBRSMAP_B		(0x110 * 2)

/* Rate table entry offsets */
#define	M_RT_PRS_PLCP_POS	10
#define	M_RT_PRS_DUR_POS	16

typedef struct shm_acparams shm_acparams_t;
struct shm_acparams {
	uint16	txop;
	uint16	cwmin;
	uint16	cwmax;
	uint16	cwcur;
	uint16	aifs;
	uint16	bslots;
	uint16	reggap;
	uint16	status;
	uint16	rsvd[8];
} PACKED;
#define M_EDCF_QLEN	(16 * 2)

#define WME_STATUS_NEWAC	(1 << 8)

/* Flags in M_HOST_FLAGS */
#define	MHF_ANTDIV		0x0001		/* Enable ucode antenna diversity help */
#define	MHF_SYMWAR		0x0002		
#define	MHF_RXPUWAR		0x0004		
#define	MHF_CCKPWR		0x0008		/* Enable 4 Db CCK power boost */
#define	MHF_BTCOEXIST		0x0010		/* Enable Bluetooth / WLAN coexistence */
#define	MHF_DCFILTWAR		0x0020		/* Enable g-mode DC canceller filter bw WAR */
#define	MHF_OFDMPWR		0x0040		/* Enable PA gain boost for OFDM frames */
#define	MHF_ACPRWAR		0x0080		/* Enable ACPR.  Disable for Japan, channel 14 */
#define	MHF_EDCF		0x0100		/* Enable EDCF access control */
#define	MHF_RESETPSMWAR		0x0200		/* TSSI reset PSM ucode war */
#define	MHF_FORCEFASTCLK	0x0400		/* Disable Slow clock request */
#define	MHF_ACI			0x0800		/* Enable ACI war: shiftbits by 2 on PHY_CRS */
#define	MHF_AWAR		0x1000		/* Toggle bit 11 of the 2060's rx-gm_updn register
						 * on rx/tx/rx transitions
						 */
#define MHF_RADARWAR		0x2000		
#define MHF_DEFKEYVALID		0x4000		/* Enable use of the default keys */
/* logical extension of M_HOST_FLAGS2 shifted left 16 bits */
#define MHF_BT4PCOEX		0x00010000	/* Bluetooth 4-priority coexistence */
#define MHF_FASTWAKE		0x00020000	/* fast wakeup ucode */
#define MHF_SYNTHPUWAR		0x00040000	/* force VCO recal when powerup synthpu */
#define MHF_PCISLOWCLKWAR	0x00080000	
#define MHF_4318_TSSI		0x00200000	
#define MHF_TXBCMC_NOW		0x00400000	/* Flush BCMC FIFO immediately */
#define MHF_HWPWRCTL		0x00800000	/* Enable hw power control */
#define MHF_BTCMOD		0x01000000	/* BTC in alternate pins */
#define MHF_TBT			0x02000000	/* enable tx bluetooth check during transmission */
#define MHF_SKIP_CFP_UPDATE	0x04000000	/* Skip CFP update */


/* phy noise recorded by ucode right after tx */
#define	M_PHY_NOISE		(0x037 * 2)
#define	PHY_NOISE_MASK		0x00ff

/* Receive Frame Data Header for 802.11b DCF-only frames */
typedef struct d11rxhdr d11rxhdr_t;
struct d11rxhdr {
	uint16	RxFrameSize;		/* Actual byte length of the frame data received */
	uint16	PAD;			/* Reserved */
	uint16	PhyRxStatus_0;		/* PhyRxStatus 15:0 */
	uint16	PhyRxStatus_1;		/* PhyRxStatus 31:16 */
	uint16	PhyRxStatus_2;		/* PhyRxStatus 47:32 */
	uint16	PhyRxStatus_3;		/* PhyRxStatus 63:48 */
	uint16	RxStatus1;		/* MAC Rx Status */
	uint16	RxStatus2;		/* extended MAC Rx status */
	uint16	RxTSFTime;		/* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
	uint16	RxChan;			/* gain code, channel radio code, and phy type */
} PACKED;

#define	RXHDR_LEN		20	/* sizeof d11rxhdr_t */

#define	FRAMELEN(h)		((h)->RxFrameSize)

/* PhyRxStatus_0: */
#define	PRXS0_GAIN_CTL		0x4000
#define	PRXS0_PLCPHCF		0x0200
#define	PRXS0_PLCPFV		0x0100
#define	PRXS0_SHORTH		0x0080
#define	PRXS0_LCRS		0x0040
#define	PRXS0_RXANT		0x0020	/* NPHY: upper sideband */
#define	PRXS0_UNSRATE		0x0010
#define	PRXS0_CLIP_MASK		0x000C
#define	PRXS0_CLIP_SHIFT	2
#define	PRXS0_FT_MASK		0x0003
#define	PRXS0_CCK		0x0000
#define	PRXS0_OFDM		0x0001	/* valid only for G phy, use rxh->RxChan for A phy */
#define	PRXS0_PREN		0x0002
#define	PRXS0_STDN		0x0003

/* PhyRxStatus_1: */
#define	PRXS1_SQ_MASK		0xff00
#define	PRXS1_SQ_SHIFT		8
#define	PRXS1_JSSI_MASK		0x00ff
#define	PRXS1_JSSI_SHIFT	0

/* PhyRxStatus_2: */
#define	PRXS2_LNAGN_MASK	0xc000
#define	PRXS2_LNAGN_SHIFT	14
#define	PRXS2_PGAGN_MASK	0x3c00
#define	PRXS2_PGAGN_SHIFT	10
#define	PRXS2_FOFF_MASK		0x03ff

/* PhyRxStatus_3: */
#define	PRXS3_DIGGN_MASK	0x1800
#define	PRXS3_DIGGN_SHIFT	11
#define	PRXS3_TRSTATE		0x0400

/* RxStatus1: */
#define	RXS_BCNSENT		0x8000
#define	RXS_SECKINDX_MASK	0x07e0
#define	RXS_SECKINDX_SHIFT	5
#define	RXS_DECERR		(1 << 4)
#define	RXS_DECATMPT		(1 << 3)
#define	RXS_PBPRES		(1 << 2)	/* PAD bytes to make IP data 4 bytes aligned */
#define	RXS_RESPFRAMETX		(1 << 1)
#define	RXS_FCSERR		(1 << 0)

/* RxChan */
#define	RXS_CHAN_GAIN_MASK	0xfc00
#define	RXS_CHAN_GAIN_SHIFT	10
#define	RXS_CHAN_ID_MASK	0x03fc
#define	RXS_CHAN_ID_SHIFT	2
#define	RXS_CHAN_PHYTYPE_MASK	0x0003
#define	RXS_CHAN_PHYTYPE_SHIFT	0

/* PSM SHM variable offsets */
#define	M_PSM_SOFT_REGS	0x0
#define	M_BOM_REV_MAJOR	(M_PSM_SOFT_REGS + 0x0)
#define	M_BOM_REV_MINOR	(M_PSM_SOFT_REGS + 0x2)
#define	M_UCODE_DATE	(M_PSM_SOFT_REGS + 0x4)		/* 4:4:8 year:month:day format */
#define	M_UCODE_TIME	(M_PSM_SOFT_REGS + 0x6)		/* 5:6:5 hour:min:sec format */
#define	M_UCODE_DBGST	(M_PSM_SOFT_REGS + 0x40)	/* ucode debug status code */
#define	M_UCODE_MACSTAT	(M_PSM_SOFT_REGS + 0xE0)	/* macstat counters */

#define	M_MBURST_SIZE	(0x40 * 2)			/* max frames in a frameburst */
#define M_SYNTHPU_DLY	(0x4a * 2)			/* pre-wakeup for synthpu, default: 500 */
#define	M_PRETBTT	(0x4b * 2)


/* ucode debug status codes */
#define	DBGST_INACTIVE		0		/* not valid really */
#define	DBGST_INIT		1		/* after zeroing SHM, before suspending at init */
#define	DBGST_ACTIVE		2		/* "normal" state */
#define	DBGST_SUSPENDED		3		/* suspended */
#define	DBGST_ASLEEP		4		/* asleep (PS mode) */

/* Scratch Reg defs */
#define	S_DOT11_CWMIN		3		/* Contention window min */
#define	S_DOT11_CWMAX		4		/* Contention window max */
#define	S_DOT11_CWCUR		5		/* Contention window current */
#define	S_DOT11_SRC_LMT		6		/* short retry count limit */
#define	S_DOT11_LRC_LMT		7		/* long retry count limit */
#define	S_DOT11_DTIMCOUNT	8		/* current DTIM count */
#define	S_BCN0_FRM_BYTESZ	21		/* Beacon 0 template length */
#define	S_BCN1_FRM_BYTESZ	22		/* Beacon 1 template length */
#define	S_SFRMTXCNTFBRTHSD	23		/* short frame tx count threshold for rate
						 * fallback
						 */
#define	S_LFRMTXCNTFBRTHSD	24		/* long frame tx count threshold */

/* IHR offsets */
#define TSF_TMR_TSF_L		0x119
#define TSF_TMR_TSF_ML		0x11A
#define TSF_TMR_TSF_MU		0x11B
#define TSF_TMR_TSF_H		0x11C

#define TSF_GPT_0_STAT		0x123
#define TSF_GPT_1_STAT		0x124
#define TSF_GPT_0_CTR_L		0x125
#define TSF_GPT_1_CTR_L		0x126
#define TSF_GPT_0_CTR_H		0x127
#define TSF_GPT_1_CTR_H		0x128
#define TSF_GPT_0_VAL_L		0x129
#define TSF_GPT_1_VAL_L		0x12A
#define TSF_GPT_0_VAL_H		0x12B
#define TSF_GPT_1_VAL_H		0x12C

/* GPT_2 is corerev >= 3 */
#define TSF_GPT_2_STAT		0x133
#define TSF_GPT_2_CTR_L		0x134
#define TSF_GPT_2_CTR_H		0x135
#define TSF_GPT_2_VAL_L		0x136
#define TSF_GPT_2_VAL_H		0x137

/* IHR TSF_GPT STAT values */
#define TSF_GPT_PERIODIC	(1 << 12)
#define TSF_GPT_ADJTSF		(1 << 13)
#define TSF_GPT_USETSF		(1 << 14)
#define TSF_GPT_ENABLE		(1 << 15)

/* ucode mac statistic counters in shared memory */
typedef struct macstat {
	uint16	txallfrm;		/* 0x80 */
	uint16	txrtsfrm;		/* 0x82 */
	uint16	txctsfrm;		/* 0x84 */
	uint16	txackfrm;		/* 0x86 */
	uint16	txdnlfrm;		/* 0x88 */
	uint16	txbcnfrm;		/* 0x8a */
	uint16	txfunfl[8];		/* 0x8c - 0x9b */
	uint16	txtplunfl;		/* 0x9c */
	uint16	txphyerr;		/* 0x9e */
	uint16	PAD[2];
	uint16	rxfrmtoolong;		/* 0xa4 */
	uint16	rxfrmtooshrt;		/* 0xa6 */
	uint16	rxinvmachdr;		/* 0xa8 */
	uint16	rxbadfcs;		/* 0xaa */
	uint16	rxbadplcp;		/* 0xac */
	uint16	rxcrsglitch;		/* 0xae */
	uint16	rxstrt;			/* 0xb0 */
	uint16	rxdfrmucastmbss;	/* 0xb2 */
	uint16	rxmfrmucastmbss;	/* 0xb4 */
	uint16	rxcfrmucast;		/* 0xb6 */
	uint16	rxrtsucast;		/* 0xb8 */
	uint16	rxctsucast;		/* 0xba */
	uint16	rxackucast;		/* 0xbc */
	uint16	rxdfrmocast;		/* 0xbe */
	uint16	rxmfrmocast;		/* 0xc0 */
	uint16	rxcfrmocast;		/* 0xc2 */
	uint16	rxrtsocast;		/* 0xc4 */
	uint16	rxctsocast;		/* 0xc6 */
	uint16	rxdfrmmcast;		/* 0xc8 */
	uint16	rxmfrmmcast;		/* 0xca */
	uint16	rxcfrmmcast;		/* 0xcc */
	uint16	rxbeaconmbss;		/* 0xce */
	uint16	rxdfrmucastobss;	/* 0xd0 */
	uint16	rxbeaconobss;		/* 0xd2 */
	uint16	rxrsptmout;		/* 0xd4 */
	uint16	bcntxcancl;		/* 0xd6 */
	uint16	PAD;
	uint16	rxf0ovfl;		/* 0xda */
	uint16	rxf1ovfl;		/* 0xdc */
	uint16	rxf2ovfl;		/* 0xde */
	uint16	txsfovfl;		/* 0xe0 */
	uint16	pmqovfl;		/* 0xe2 */
	uint16	rxcgprqfrm;		/* 0xe4 */
	uint16	rxcgprsqovfl;		/* 0xe6 */
	uint16	txcgprsfail;		/* 0xe8 */
	uint16	txcgprssuc;		/* 0xea */
	uint16	prs_timeout;		/* 0xec */
	uint16	rxnack;			/* 0xee afterburner: received nacks */
	uint16	frmscons;		/* 0xf0 afterburner: frames consumed waiting requeue */
	uint16	txnack;			/* 0xf2 afterburner: transmitted nacks */
	uint16	txglitch_nack;		/* 0xf4 afterburner: subset of above */
	uint16	txburst;		/* 0xf6 # tx bursts */
	uint16	rxburst;		/* 0xf8 # rx bursts */
} macstat_t;

/* dot11 core-specific sbtmstatelow flags */
#define	SBTML_CE		((uint32)1 << 18)	/* PHY clock enable */
#define	SBTML_PR		((uint32)1 << 19)	/* PHY reset */
#define	SBTML_MP		((uint32)1 << 20)	/* MAC PHY clockcontrol enable */
#define	SBTML_FS		((uint32)1 << 21)	/* PLL FreqRefSelect (corerev >= 5) */

#define	SBTML_GM		((uint32)1 << 29)	/* gmode enable */

/* dot11 core-specific sbtmstatehigh flags */
#define	SBTMH_GA		((uint32)1 << 16)	/* GphyAvailable (corerev >= 5) */
#define	SBTMH_AA		((uint32)1 << 17)	/* AphyAvailable (corerev >= 5) */
#define	SBTMH_FCA		((uint32)1 << 18)	/* FastClkAvailable (corerev >= 5) */

#undef PACKED
#if !defined(__GNUC__)
#pragma pack()
#endif

#endif	/* _D11_H */