d11.h

wi-fi sources for asus wl138g v2 pci card

/* interrupt receive lazy */
#define	IRL_TO_MASK		0x00ffffff	/* timeout */
#define	IRL_FC_MASK		0xff000000	/* frame count */
#define	IRL_FC_SHIFT		24		/* frame count */

/* maccontrol register */
#define	MCTL_GMODE		(1 << 31)
#define	MCTL_DISCARD_PMQ	(1 << 30)
#define	MCTL_DISCARD_TXSTATUS	(1 << 29)
#define	MCTL_TBTT_HOLD		(1 << 28)
#define	MCTL_CLOSED_NETWORK	(1 << 27)
#define	MCTL_WAKE		(1 << 26)
#define	MCTL_HPS		(1 << 25)
#define	MCTL_PROMISC		(1 << 24)
#define	MCTL_KEEPBADFRAMES	(1 << 23)
#define	MCTL_KEEPCONTROL	(1 << 22)
#define	MCTL_KEEPBADPLCP	(1 << 21)
#define	MCTL_BCNS_PROMISC	(1 << 20)
#define	MCTL_LOCK_RADIO		(1 << 19)
#define	MCTL_AP			(1 << 18)
#define	MCTL_INFRA		(1 << 17)
#define	MCTL_BIGEND		(1 << 16)
#define	MCTL_GPOUT_SEL_MASK	(3 << 14)
#define	MCTL_GPOUT_SEL_SHIFT	14
#define	MCTL_EN_PSMDBG		(1 << 13)
#define	MCTL_IHR_EN		(1 << 10)
#define	MCTL_SHM_UPPER		(1 <<  9)
#define	MCTL_SHM_EN		(1 <<  8)
#define	MCTL_PSM_JMP_0		(1 <<  2)
#define	MCTL_PSM_RUN		(1 <<  1)
#define	MCTL_EN_MAC		(1 <<  0)

/* maccommand register */
#define	MCMD_BCN0VLD		(1 <<  0)
#define	MCMD_BCN1VLD		(1 <<  1)
#define	MCMD_DIRFRMQVAL		(1 <<  2)
#define	MCMD_CCA		(1 <<  3)
#define	MCMD_BG_NOISE		(1 <<  4)

/* macintstatus/macintmask */
#define	MI_MACSSPNDD		(1 <<  0)	/* MAC has gracefully suspended */
#define	MI_BCNTPL		(1 <<  1)	/* beacon template available */
#define	MI_TBTT			(1 <<  2)	/* TBTT indication */
#define	MI_BCNSUCCESS		(1 <<  3)	/* beacon succesfully tx */
#define	MI_BCNCANCLD		(1 <<  4)	/* beacon cancelled (IBSS) */
#define	MI_ATIMWINEND		(1 <<  5)	/* end of ATIM-window (IBSS) */
#define	MI_PMQ			(1 <<  6)	/* PMQ entries available */
#define	MI_NSPECGEN_0		(1 <<  7)	/* non-specific gen-stat bits that are set by PSM */
#define	MI_NSPECGEN_1		(1 <<  8)	/* non-specific gen-stat bits that are set by PSM */
#define	MI_MACTXERR		(1 <<  9)	/* MAC level Tx error */
#define	MI_NSPECGEN_3		(1 << 10)	/* non-specific gen-stat bits that are set by PSM */
#define	MI_PHYTXERR		(1 << 11)	/* PHY Tx error */
#define	MI_PME			(1 << 12)	/* Power Management Event */
#define	MI_GP0			(1 << 13)	/* General-purpose timer0 */
#define	MI_GP1			(1 << 14)	/* General-purpose timer1 */
#define	MI_DMAINT		(1 << 15)	/* (ORed) DMA-interrupts */
#define	MI_TXSTOP		(1 << 16)	/* MAC has completed a TX FIFO Suspend/Flush */
#define	MI_CCA			(1 << 17)	/* MAC has completed a CCA measurement */
#define	MI_BG_NOISE		(1 << 18)	/* MAC has collected background noise samples */
#define MI_RFDISABLE		(1 << 28)	/* MAC detected a change on RF Disable input
						 * (corerev >= 10)
						 */
#define	MI_TFS			(1 << 29)	/* MAC has completed a TX (corerev >= 5) */
#define	MI_PHYCHANGED		(1 << 30)	/* A phy status change wrt G mode */
#define	MI_TO			(1 << 31)	/* general purpose timeout (corerev >= 3) */

/* pmqhost data */
#define	PMQH_DATA_MASK		0xffff0000	/* data entry of head pmq entry */
#define	PMQH_PMOFF		0x00010000	/* PM Mode OFF: power save off */
#define	PMQH_PMON		0x00020000	/* PM Mode ON: power save on */
#define	PMQH_DASAT		0x00040000	/* Dis-associated or De-authenticated */
#define	PMQH_ATIMFAIL		0x00080000	/* ATIM not acknowledged */
#define	PMQH_DEL_ENTRY		0x00000001	/* delete head entry */
#define	PMQH_DEL_MULT		0x00000002	/* delete head entry to cur read pointer -1 */
#define	PMQH_OFLO		0x00000004	/* pmq overflow indication */
#define	PMQH_NOT_EMPTY		0x00000008	/* entries are present in pmq */


/* objaddr register */
#define	OBJADDR_SEL_MASK	0x000F0000
#define	OBJADDR_UCM_SEL		0x00000000
#define	OBJADDR_SHM_SEL		0x00010000
#define	OBJADDR_SCR_SEL		0x00020000
#define	OBJADDR_IHR_SEL		0x00030000
#define	OBJADDR_RCMTA_SEL	0x00040000
#define	OBJADDR_WINC		0x01000000
#define	OBJADDR_RINC		0x02000000
#define	OBJADDR_AUTO_INC	0x03000000

/* pcmaddr bits */
#define	PCMADDR_INC		0x4000
#define	PCMADDR_UCM_SEL		0x0000

#define	WEP_PCMADDR		0x07d4
#define	WEP_PCMDATA		0x07d6

/* frmtxstatus */
#define	TXS_V			(1 << 0)	/* valid bit */
#define	TXS_STATUS_MASK		0xffff
/* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */
#define	TXS_COMPAT_MASK		0x3
#define	TXS_COMPAT_SHIFT	1
#define	TXS_FID_MASK		0xffff0000
#define	TXS_FID_SHIFT		16

/* frmtxstatus2 */
#define	TXS_SEQ_MASK		0xffff
#define	TXS_PTX_MASK		0xff0000
#define	TXS_PTX_SHIFT		16
#define	TXS_MU_MASK		0x01000000
#define	TXS_MU_SHIFT		24

/* tsf_cfprep register */
#define	CFPREP_CBI_MASK		0xffffffc0
#define	CFPREP_CBI_SHIFT	6
#define	CFPREP_CFPP		0x00000001

/* transmit fifo control for 2-byte pio */
#define	XFC_BV_MASK		0x3		/* bytes valid */
#define	XFC_LO			(1 << 0)	/* low byte valid */
#define	XFC_HI			(1 << 1)	/* high byte valid */
#define	XFC_BOTH		(XFC_HI | XFC_LO) /* both bytes valid */
#define	XFC_EF			(1 << 2)	/* end of frame */
#define	XFC_FR			(1 << 3)	/* frame ready */
#define	XFC_FL			(1 << 5)	/* flush request */
#define	XFC_FP			(1 << 6)	/* flush pending */
#define	XFC_SE			(1 << 7)	/* suspend request */
#define	XFC_SP			(1 << 8)	
#define	XFC_CC_MASK		0xfc00		/* committed count */
#define	XFC_CC_SHIFT		10

/* transmit fifo control for 4-byte pio */
#define	XFC4_BV_MASK		0xf		/* bytes valid */
#define	XFC4_EF			(1 << 4)	/* end of frame */
#define	XFC4_FR			(1 << 7)	/* frame ready */
#define	XFC4_SE			(1 << 8)	/* suspend request */
#define	XFC4_SP			(1 << 9)	
#define	XFC4_FL			(1 << 10)	/* flush request */
#define	XFC4_FP			(1 << 11)	/* flush pending */

/* receive fifo control */
#define	RFC_FR			(1 << 0)	/* frame ready */
#define	RFC_DR			(1 << 1)	/* data ready */

/* tx fifo sizes for corerev >= 9 */
/* tx fifo sizes values are in terms of 256 byte blocks */
#define TXFIFOCMD_RESET_MASK	(1 << 15)	/* reset */
#define TXFIFOCMD_FIFOSEL_SHIFT	8		/* fifo */
#define TXFIFO_FIFOTOP_SHIFT	8		/* fifo start */

#define TXFIFO_START_BLK	 6		/* Base address + 6 * 256 B */
#define TXFIFO_SIZE_UNIT	256		/* one unit corresponds to 256 bytes */

/* PhyVersion regiser */

/* phy versions, PhyVersion:Revision field */
#define	PV_AV_MASK		0xf000		/* analog block version */
#define	PV_AV_SHIFT		12		/* analog block version bitfield offset */
#define	PV_PT_MASK		0x0f00		/* phy type */
#define	PV_PT_SHIFT		8		/* phy type bitfield offset */
#define	PV_PV_MASK		0x000f		/* phy version */
#define	PHY_TYPE(v)		((v & PV_PT_MASK) >> PV_PT_SHIFT)

/* phy types, PhyVersion:PhyType field */
#define	PHY_TYPE_A		0	/* A-Phy value */
#define	PHY_TYPE_B		1	/* B-Phy value */
#define	PHY_TYPE_G		2	/* G-Phy value */
#define	PHY_TYPE_NULL		0xf	/* Invalid Phy value */

/* analog types, PhyVersion:AnalogType field */
#define	ANA_11G_018		1
#define	ANA_11G_018_ALL		2
#define	ANA_11G_018_ALLI	3
#define	ANA_11G_013		4
#define	ANA_11N_013		5

/* 802.11a PLCP header def */
typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
struct ofdm_phy_hdr {
	uint8	rlpt[3];	/* rate, length, parity, tail */
	uint16	service;
	uint8	pad;
} PACKED;

#define	D11A_PHY_HDR_GRATE(phdr)	((phdr)->rlpt[0] & 0x0f)
#define	D11A_PHY_HDR_GRES(phdr)		(((phdr)->rlpt[0] >> 4) & 0x01)
#define	D11A_PHY_HDR_GLENGTH(phdr)	(((uint32 *)((phdr)->rlpt) >> 5) & 0x0fff)
#define	D11A_PHY_HDR_GPARITY(phdr)	(((phdr)->rlpt[3] >> 1) & 0x01)
#define	D11A_PHY_HDR_GTAIL(phdr)	(((phdr)->rlpt[3] >> 2) & 0x3f)

/* rate encoded per 802.11a-1999 sec 17.3.4.1 */
#define	D11A_PHY_HDR_SRATE(phdr, rate)		\
	((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
/* set reserved field to zero */
#define	D11A_PHY_HDR_SRES(phdr)		((phdr)->rlpt[0] &= 0xef)
/* length is number of octets in PSDU */
#define	D11A_PHY_HDR_SLENGTH(phdr, length)	\
	(*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \
	(((length) & 0x0fff) << 5))
/* set the tail to all zeros */
#define	D11A_PHY_HDR_STAIL(phdr)	((phdr)->rlpt[3] &= 0x03)

#define	D11A_PHY_HDR_LEN_L	3	/* low-rate part of PLCP header */
#define	D11A_PHY_HDR_LEN_R	2	/* high-rate part of PLCP header */

#define	D11A_PHY_TX_DELAY	(2) /* 2.1 usec */

#define	D11A_PHY_HDR_TIME	(4)	/* low-rate part of PLCP header */
#define	D11A_PHY_PRE_TIME	(16)
#define	D11A_PHY_PREHDR_TIME	(D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)

/* 802.11b PLCP header def */
typedef struct cck_phy_hdr cck_phy_hdr_t;
struct cck_phy_hdr {
	uint8	signal;
	uint8	service;
	uint16	length;
	uint16	crc;
} PACKED;

#define	D11B_PHY_HDR_LEN	6

#define	D11B_PHY_TX_DELAY	(3) /* 3.4 usec */

#define	D11B_PHY_LHDR_TIME	(D11B_PHY_HDR_LEN << 3)
#define	D11B_PHY_LPRE_TIME	(144)
#define	D11B_PHY_LPREHDR_TIME	(D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)

#define	D11B_PHY_SHDR_TIME	(D11B_PHY_LHDR_TIME >> 1)
#define	D11B_PHY_SPRE_TIME	(D11B_PHY_LPRE_TIME >> 1)
#define	D11B_PHY_SPREHDR_TIME	(D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)

#define	D11B_PLCP_SIGNAL_LOCKED	(1 << 2)
#define	D11B_PLCP_SIGNAL_LE	(1 << 7)


/* The dot11a PLCP header is 5 bytes.  To simplify the software (so that we
 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
 * padding added in the ucode.
 */
#define	D11_PHY_HDR_LEN	6

/* TX DMA buffer header */
typedef struct d11txh d11txh_t;
struct d11txh {
	uint16	MacTxControlLow;
	uint16	MacTxControlHigh;
	uint16	MacFrameControl;
	uint16	TxFesTimeNormal;
	uint16	PhyTxControlWord;
	uint16	PhyTxControlWord_1;
	uint16	PhyTxControlWord_1_Fbr;
	uint16	PhyTxControlWord_1_Rts;
	uint16	PhyTxControlWord_1_FbrRts;
	uint16	MainRates;
	uint16	XtraFrameTypes;
	uint8	IV[16];
	uint8	TxFrameRA[6];
	uint16	TxFesTimeFallback;
	uint8	RTSPLCPFallback[6];
	uint16	RTSDurFallback;
	uint8	FragPLCPFallback[6];
	uint16	FragDurFallback;
	uint16	MMDurTime;
	uint16	MMFbrDurTime;
	uint16	TstampLow;
	uint16	TstampHigh;
	uint16	PAD;
	uint16	TxFrameID;
	uint16	TxStatus;
	uint8	RTSPhyHeader[D11_PHY_HDR_LEN];
	struct dot11_rts_frame rts_frame;
	uint16	PAD;
} PACKED;

#define	D11_TXH_LEN		0x64

/* Frame Types */
#define FT_CCK	0
#define FT_OFDM	1

/* MacTxControlLow */
#define TXC_LIFETIME		0x1000
#define	TXC_FRAMEBURST		0x0800
#define	TXC_SENDCTS		0x0400
#define TXC_AMPDU_MASK		0x0300
#define TXC_FREQBAND_5G		0x0080
#define	TXC_IGNOREPMQ		0x0020
#define	TXC_HWSEQ		0x0010
#define	TXC_STARTMSDU		0x0008
#define	TXC_SENDRTS		0x0004
#define	TXC_LONGFRAME		0x0002
#define	TXC_IMMEDACK		0x0001

/* MacTxControlHigh */
#define	TXC_SECKEY_MASK		0x0FF0
#define	TXC_SECKEY_SHIFT	4
#define	TXC_SECTYPE_MASK	0x0007
#define	TXC_SECTYPE_SHIFT	0

/* PhyTxControl */
#define	PHY_TXC_ANT_MASK	0x03C0
#define	PHY_TXC_ANT_SHIFT	6
#define	PHY_TXC_ANT_LAST	0x00C0
#define	PHY_TXC_ANT_3		0x0200
#define	PHY_TXC_ANT_2		0x0100
#define	PHY_TXC_ANT_1		0x0080
#define	PHY_TXC_ANT_0		0x0040
#define	PHY_TXC_SHORT_HDR	0x0010
#define	PHY_TXC_OFDM		0x0001

#define	PHY_TXC_OLD_ANT_0	0x0000
#define	PHY_TXC_OLD_ANT_1	0x0100
#define	PHY_TXC_OLD_ANT_LAST	0x0300

/* XtraFrameTypes */
#define XFTS_RTS_FT_SHIFT	2
#define XFTS_FBRRTS_FT_SHIFT	4
#define XFTS_CHANNEL_SHIFT	8



/* IFS ctl */
#define IFS_USEEDCF	(1 << 2)

/* tx status packet */
typedef struct tx_status tx_status_t;
struct tx_status {
	uint16 framelen;
	uint16 PAD;
	uint16 frameid;
	uint16 status;
	uint16 lasttxtime;
	uint16 sequence;
	uint16 phyerr;
	uint16 ackphyrxsh;
} PACKED;

#define	TXSTATUS_LEN	16

/* status field bit definitions */
#define	TX_STATUS_FRM_RTX_MASK	0xF000
#define	TX_STATUS_FRM_RTX_SHIFT	12
#define	TX_STATUS_RTS_RTX_MASK	0x0F00
#define	TX_STATUS_RTS_RTX_SHIFT	8
#define TX_STATUS_MASK		0x00FE
#define	TX_STATUS_PMINDCTD	(1 << 7)	/* PM mode indicated to AP */
#define	TX_STATUS_INTERMEDIATE	(1 << 6)	/* Intermediate status */
#define	TX_STATUS_AMPDU		(1 << 5)	/* AMPDU status */
#define TX_STATUS_SUPR_MASK	0x1C		/* suppress status bits (4:2) */
#define TX_STATUS_SUPR_SHIFT	2
#define	TX_STATUS_ACK_RCV	(1 << 1)	/* ACK received */
#define	TX_STATUS_VALID		(1 << 0)	/* Tx status valid (corerev >= 5) */
#define	TX_STATUS_NO_ACK	0

/* suppress status reason codes */
#define	TX_STATUS_SUPR_PMQ	(1 << 2)	/* PMQ entry */
#define	TX_STATUS_SUPR_FLUSH	(2 << 2)	/* flush request */
#define	TX_STATUS_SUPR_FRAG	(3 << 2)	/* previous frag failure */
#define	TX_STATUS_SUPR_BADCH	(4 << 2)	/* channel mismatch */
#define	TX_STATUS_SUPR_EXPTIME	(5 << 2)	/* lifetime expiry */
#define	TX_STATUS_SUPR_UF	(6 << 2)	/* underflow */
#define	TX_STATUS_SUPR_NACK	(7 << 2)	/* afterburner NACK */

/* Unexpected tx status for rate update */
#define TX_STATUS_UNEXP(status) \
	(((status & (TX_STATUS_SUPR_MASK | TX_STATUS_INTERMEDIATE)) != 0) && \
	 ((status & (TX_STATUS_SUPR_MASK | TX_STATUS_INTERMEDIATE)) !=  TX_STATUS_SUPR_EXPTIME) && \
	  ((status & (TX_STATUS_SUPR_MASK | TX_STATUS_INTERMEDIATE)) !=  TX_STATUS_SUPR_NACK))

/* RXE (Receive Engine) */

/* RCM_CTL */
#define	RCM_INC_MASK_H		0x0080
#define	RCM_INC_MASK_L		0x0040
#define	RCM_INC_DATA		0x0020
#define	RCM_INDEX_MASK		0x001F

#define	RCM_MAC_OFFSET		0
#define	RCM_BSSID_OFFSET	3
#define	RCM_WEP_TA0_OFFSET	16
#define	RCM_WEP_TA1_OFFSET	19
#define	RCM_WEP_TA2_OFFSET	22
#define	RCM_WEP_TA3_OFFSET	25

/* WEP Block */

/* WEP_WKEY */
#define	WKEY_START		(1 << 8)
#define	WKEY_SEL_MASK		0x1F

/* WEP data formats */

/* max keys in M_SECTXKEYS_BLK and M_SECRXKEYS_BLK */
#define	WSEC_MAX_SEC_KEYS	16	/* 12 + 4 default */

/* max keys in rcmta block */
#define	WSEC_MAX_RCMTA_KEYS	54

/* max RXE match registers */
#define	WSEC_MAX_RXE_KEYS	4

/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
/* SKL (Security Key Lookup) */
#define	SKL_INDEX_MASK		0xF0