d11.h

wi-fi sources for asus wl138g v2 pci card

/*
 * Chip-specific hardware definitions for
 * Broadcom 802.11abg Networking Device Driver
 *
 * Copyright 2005-2006, Broadcom Corporation
 * All Rights Reserved.                
 *                                     
 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
 *
 * $Id$
 */

#ifndef	_D11_H
#define	_D11_H

#include <bcmdevs.h>
#include <sbconfig.h>


/* enable structure packing */
#if defined(__GNUC__)
#define	PACKED	__attribute__((packed))
#else
#pragma pack(1)
#define	PACKED
#endif

/* cpp contortions to concatenate w/arg prescan */
#ifndef	PAD
#define	_PADLINE(line)	pad ## line
#define	_XSTR(line)	_PADLINE(line)
#define	PAD		_XSTR(__LINE__)
#endif

#define	BCN_TMPL_LEN		512	/* length of the BCN template area */

/* RX FIFO numbers */
#define	RX_FIFO			0	/* data and ctl frames */
#define	RX_TXSTATUS_FIFO	3	/* RX fifo for tx status packages */

/* TX FIFO numbers using WME Access Classes */
#define	TX_AC_BK_FIFO		0	/* Access Category Background TX FIFO */
#define	TX_AC_BE_FIFO		1	/* Access Category Best-Effort TX FIFO */
#define TX_AC_VI_FIFO		2	/* Access Class Video TX FIFO */
#define	TX_AC_VO_FIFO		3	/* Access Class Voice TX FIFO */
#define	TX_BCMC_FIFO		4	/* Broadcast/Multicast TX FIFO */
#define	TX_ATIM_FIFO		5	/* TX fifo for ATIM window info */

/* Legacy TX FIFO numbers */
#define	TX_DATA_FIFO		TX_AC_BE_FIFO
#define	TX_CTL_FIFO		TX_AC_VO_FIFO


/* delay from end of PLCP reception to RxTSFTime */
#define	M_APHY_PLCPRX_DLY	3
#define	M_BPHY_PLCPRX_DLY	4


typedef volatile struct {
	uint32	intstatus;
	uint32	intmask;
} intctrlregs_t;

/* read: 32-bit register that can be read as 32-bit or as 2 16-bit
 * write: only low 16b-it half can be written
 */
typedef volatile union {
	uint32 pmqhostdata;		/* read only! */
	struct {
		uint16 pmqctrlstatus;	/* read/write */
		uint16 PAD;
	} w;
} pmqreg_t;

/* pio register set 2/4 bytes union for d11 fifo */
typedef volatile union {
	pio2regp_t	b2;		/* < corerev 8 */
	pio4regp_t	b4;		/* >= corerev 8 */
} u_pioreg_t;

/* dma/pio corerev < 11 */
typedef volatile struct {
	dma32regp_t	dmaregs[8];	/* 0x200 - 0x2fc */
	u_pioreg_t	pioregs[8];	/* 0x300 */
} fifo32_t;

/* dma/pio corerev >= 11 */
typedef volatile struct {
	dma64regs_t	dmaxmt;		/* dma tx */
	pio4regs_t	piotx;		/* pio tx */
	dma64regs_t	dmarcv;		/* dma rx */
	pio4regs_t	piorx;		/* pio rx */
} fifo64_t;

/*
 * Host Interface Registers
 * - but definitely not complete
 */
typedef volatile struct _d11regs {
	/* Device Control ("semi-standard host registers") */
	uint32	PAD[3];			/* 0x0 - 0x8 */
	uint32	biststatus;		/* 0xC */
	uint32	biststatus2;		/* 0x10 */
	uint32	PAD;			/* 0x14 */
	uint32	gptimer;		/* 0x18 */	/* for corerev >= 3 */
	uint32	PAD;			/* 0x1c */

	/* Interrupt Control */		/* 0x20 */
	intctrlregs_t	intctrlregs[8];

	uint32	PAD[40];		/* 0x60 - 0xFC */

	/* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
	uint32	intrcvlazy[4];		/* 0x100 - 0x10C */

	uint32	PAD[4];			/* 0x110 - 0x11c */

	uint32	maccontrol;		/* 0x120 */
	uint32	maccommand;		/* 0x124 */
	uint32	macintstatus;		/* 0x128 */
	uint32	macintmask;		/* 0x12C */

	/* Transmit Template Access */
	uint32	tplatewrptr;		/* 0x130 */
	uint32	tplatewrdata;		/* 0x134 */
	uint32	PAD[2];			/* 0x138 - 0x13C */

	/* PMQ registers */
	pmqreg_t pmqreg;		/* 0x140 */
	uint32	pmqpatl;		/* 0x144 */
	uint32	pmqpath;		/* 0x148 */
	uint32	PAD;			/* 0x14C */

	uint32	chnstatus;		/* 0x150 */
	uint32	psmdebug;		/* 0x154 */	/* for corerev >= 3 */
	uint32	phydebug;		/* 0x158 */	/* for corerev >= 3 */
	uint32	PAD;			/* 0x15C */

	/* Extended Internal Objects */
	uint32	objaddr;		/* 0x160 */
	uint32	objdata;		/* 0x164 */
	uint32	PAD[2];			/* 0x168 - 0x16c */

	/* New txstatus registers on corerev >= 5 */
	uint32	frmtxstatus;		/* 0x170 */
	uint32	frmtxstatus2;		/* 0x174 */
	uint32	PAD[2];			/* 0x178 - 0x17c */

	/* New TSF host access on corerev >= 3 */

	uint32	tsf_timerlow;		/* 0x180 */
	uint32	tsf_timerhigh;		/* 0x184 */
	uint32	tsf_cfprep;		/* 0x188 */
	uint32	tsf_cfpstart;		/* 0x18c */
	uint32	tsf_cfpmaxdur32;	/* 0x190 */
	uint32	PAD[27];		/* 0x194 - 0x1fc */

	/* 0x200-0x37F dma/pio registers */
	volatile union {
		fifo32_t	f32regs;	/* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */
		fifo64_t	f64regs[6];	/* on corerev >= 11 */
	} fifo;

	/* FIFO diagnostic port access */
	dma32diag_t dmafifo;		/* 0x380 - 0x38C */

	uint32	PAD[19];		/* 0x390 - 0x3D8 */

	/* time delay between the change on rf disable input and radio shutdown corerev 10 */
	uint32  rfdisabledly;		/* 0x3DC */

	/* PHY register access */
	uint16	phyversion;		/* 0x3e0 - 0x0 */
	uint16	phybbconfig;		/* 0x3e2 - 0x1 */
	uint16	phyadcbias;		/* 0x3e4 - 0x2 */
	uint16	phy0;			/* 0x3e6 - 0x3 */
	uint16	phyrxstatus0;		/* 0x3e8 - 0x4 */
	uint16	phyrxstatus1;		/* 0x3ea - 0x5 */
	uint16	phy1;			/* 0x3ec - 0x6 */
	uint16	phytxerror;		/* 0x3ee - 0x7 */
	uint16	phy5;			/* 0x3f0 - 0x8 */
	uint16	PAD[1];			/* 0x3f2 - 0x9 */
	uint16	phytest;		/* 0x3f4 - 0xa */
	uint16	phy2;			/* 0x3f6 - 0xb */
	uint16	phy3;			/* 0x3f8 - 0xc */
	uint16	phy4;			/* 0x3fa - 0xd */
	uint16	phyregaddr;		/* 0x3fc - 0xe */
	uint16	phyregdata;		/* 0x3fe - 0xf */

	/* IHR */			/* 0x400 - 0x7FE */

	/* RXE Block */
	uint16	PAD[3];			/* 0x400 - 0x406 */
	uint16	rcv_fifo_ctl;		/* 0x406 */
	uint16	PAD;			/* 0x408 - 0x40a */
	uint16	rcv_frm_cnt;		/* 0x40a */
	uint16	PAD[0xa];		/* 0x40a - 0x420 */
	uint16	rcm_ctl;		/* 0x420 */
	uint16	rcm_mat_data;		/* 0x422 */
	uint16	rcm_mat_mask;		/* 0x424 */
	uint16	rcm_mat_dly;		/* 0x426 */
	uint16	rcm_cond_mask_l;	/* 0x428 */
	uint16	rcm_cond_mask_h;	/* 0x42A */
	uint16	rcm_cond_dly;		/* 0x42C */
	uint16	PAD[1];			/* 0x42E */
	uint16	ext_ihr_addr;		/* 0x430 */
	uint16	ext_ihr_data;		/* 0x432 */
	uint16	rxe_phyrs_2;		/* 0x434 */
	uint16	rxe_phyrs_3;		/* 0x436 */
	uint16	phy_mode;		/* 0x438 */
	uint16	rcmta_ctl;		/* 0x43a */
	uint16	rcmta_size;		/* 0x43c */
	uint16	rcmta_addr0;		/* 0x43e */
	uint16	rcmta_addr1;		/* 0x440 */
	uint16	rcmta_addr2;		/* 0x442 */
	uint16	PAD[30];		/* 0x444 - 0x480 */

	/* PSM Block */			/* 0x480 - 0x500 */

	uint16 PAD;			/* 0x480 */
	uint16 psm_maccontrol_h;	/* 0x482 */
	uint16 psm_macintstatus_l;	/* 0x484 */
	uint16 psm_macintstatus_h;	/* 0x486 */
	uint16 psm_macintmask_l;	/* 0x488 */
	uint16 psm_macintmask_h;	/* 0x48A */
	uint16 PAD;			/* 0x48C */
	uint16 psm_maccommand;		/* 0x48E */
	uint16 psm_brc;			/* 0x490 */
	uint16 psm_phy_hdr_param;	/* 0x492 */
	uint16 psm_postcard;		/* 0x494 */
	uint16 psm_pcard_loc_l;		/* 0x496 */
	uint16 psm_pcard_loc_h;		/* 0x498 */
	uint16 psm_gpio_in;		/* 0x49A */
	uint16 psm_gpio_out;		/* 0x49C */
	uint16 psm_gpio_oe;		/* 0x49E */

	uint16 psm_bred_0;		/* 0x4A0 */
	uint16 psm_bred_1;		/* 0x4A2 */
	uint16 psm_bred_2;		/* 0x4A4 */
	uint16 psm_bred_3;		/* 0x4A6 */
	uint16 psm_brcl_0;		/* 0x4A8 */
	uint16 psm_brcl_1;		/* 0x4AA */
	uint16 psm_brcl_2;		/* 0x4AC */
	uint16 psm_brcl_3;		/* 0x4AE */
	uint16 psm_brpo_0;		/* 0x4B0 */
	uint16 psm_brpo_1;		/* 0x4B2 */
	uint16 psm_brpo_2;		/* 0x4B4 */
	uint16 psm_brpo_3;		/* 0x4B6 */
	uint16 psm_brwk_0;		/* 0x4B8 */
	uint16 psm_brwk_1;		/* 0x4BA */
	uint16 psm_brwk_2;		/* 0x4BC */
	uint16 psm_brwk_3;		/* 0x4BE */

	uint16 psm_base_0;		/* 0x4C0 */
	uint16 psm_base_1;		/* 0x4C2 */
	uint16 psm_base_2;		/* 0x4C4 */
	uint16 psm_base_3;		/* 0x4C6 */
	uint16 psm_base_4;		/* 0x4C8 */
	uint16 psm_base_5;		/* 0x4CA */
	uint16 psm_base_6;		/* 0x4CC */
	uint16 psm_pc_reg_0;		/* 0x4CE */
	uint16 psm_pc_reg_1;		/* 0x4D0 */
	uint16 psm_pc_reg_2;		/* 0x4D2 */
	uint16 psm_pc_reg_3;		/* 0x4D4 */
	uint16 PAD[0x15];		/* 0x4D6 - 0x4FE */

	/* TXE0 Block */		/* 0x500 - 0x580 */
	uint16	txe_ctl;		/* 0x500 */
	uint16	txe_aux;		/* 0x502 */
	uint16	txe_ts_loc;		/* 0x504 */
	uint16	txe_time_out;		/* 0x506 */
	uint16	txe_wm_0;		/* 0x508 */
	uint16	txe_wm_1;		/* 0x50A */
	uint16	txe_phyctl;		/* 0x50C */
	uint16	txe_status;		/* 0x50E */

	uint16	PAD[0x08];		/* 0x510 - 0x51E */

	/* Transmit control */
	uint16  xmtfifodef;		/* 0x520 */

	uint16  PAD[0x0F];		/* 0x522 - 0x53E */

	uint16	xmtfifocmd;		/* 0x540 */
	uint16	xmtfifoflush;		/* 0x542 */
	uint16	xmtfifothresh;		/* 0x544 */
	uint16	xmtfifordy;		/* 0x546 */
	uint16	xmtfifoprirdy;		/* 0x548 */
	uint16	xmtfiforqpri;		/* 0x54A */
	uint16	xmttplatetxptr;		/* 0x54C */
	uint16	PAD;			/* 0x54E */
	uint16	xmttplateptr;		/* 0x550 */

	uint16	PAD[0x07];		/* 0x552 - 0x55E */

	uint16	xmttplatedatalo;	/* 0x560 */
	uint16	xmttplatedatahi;	/* 0x562 */

	uint16	PAD[2];			/* 0x564 - 0x566 */

	uint16	xmtsel;			/* 0x568 */
	uint16	xmttxcnt;		/* 0x56A */
	uint16	xmttxshmaddr;		/* 0x56C */

	uint16	PAD[0x09];		/* 0x56E - 0x57E */

	/* TXE1 Block */
	uint16	PAD[0x40];		/* 0x580 - 0x5FE */

	/* TSF Block */
	uint16	PAD[0X02];		/* 0x600 - 0x602 */
	uint16	tsf_cfpstrt_l;		/* 0x604 */
	uint16	tsf_cfpstrt_h;		/* 0x606 */
	uint16	PAD[0X05];		/* 0x608 - 0x610 */
	uint16	tsf_cfppretbtt;		/* 0x612 */
	uint16	PAD[0X23];		/* 0x614 - 0x658 */
	uint16	tsf_random;		/* 0x65A */
	uint16	PAD[0x05];		/* 0x65C - 0x664 */
	/* GPTimer 2 registers are corerev >= 3 */
	uint16	tsf_gpt2_stat;		/* 0x666 */
	uint16	tsf_gpt2_ctr_l;		/* 0x668 */
	uint16	tsf_gpt2_ctr_h;		/* 0x66A */
	uint16	tsf_gpt2_val_l;		/* 0x66C */
	uint16	tsf_gpt2_val_h;		/* 0x66E */
	uint16	tsf_gptall_stat;	/* 0x670 */
	uint16	PAD[0x07];		/* 0x672 - 0x67E */

	/* IFS Block */
	uint16	ifs_sifs_rx_tx_tx;	/* 0x680 */
	uint16	ifs_sifs_nav_tx;	/* 0x682 */
	uint16	ifs_slot;		/* 0x684 */
	uint16	PAD;			/* 0x686 */
	uint16	ifs_ctl;		/* 0x688 */
	uint16	PAD[0x3];		/* 0x68a - 0x68F */
	uint16	ifsstat;		/* 0x690 */
	uint16	ifsmedbusyctl;		/* 0x692 */
	uint16	iftxdur;		/* 0x694 */
	uint16	PAD[5];
		/* New slow clock registers on corerev >= 5 */
	uint16	scc_ctl;		/* 0x6a0 */
	uint16	scc_timer_l;		/* 0x6a2 */
	uint16	scc_timer_h;		/* 0x6a4 */
	uint16	scc_frac;		/* 0x6a6 */
	uint16	scc_fastpwrup_dly;	/* 0x6a8 */
	uint16	scc_per;		/* 0x6aa */
	uint16	scc_per_frac;		/* 0x6ac */
	uint16	PAD[41];		/* 0x6ad - 0x6FF */

	/* NAV Block */
	uint16	nav_ctl;		/* 0x700 */
	uint16	navstat;		/* 0x702 */
	uint16	PAD[0x3e];		/* 0x702 - 0x77E */

	/* WEP/PMQ Block */		/* 0x780 - 0x7FE */
	uint16 PAD[0x20];		/* 0x780 - 0x7BE */

	uint16 wepctl;			/* 0x7C0 */
	uint16 wepivloc;		/* 0x7C2 */
	uint16 wepivkey;		/* 0x7C4 */
	uint16 wepwkey;			/* 0x7C6 */

	uint16 PAD[0x0C];		/* 0x7C8 - 0x7DE */

	uint16 pmqctl;			/* 0x7E0 */
	uint16 pmqstatus;		/* 0x7E2 */
	uint16 pmqpat0;			/* 0x7E4 */
	uint16 pmqpat1;			/* 0x7E6 */
	uint16 pmqpat2;			/* 0x7E8 */

	uint16 pmqdat;			/* 0x7EA */
	uint16 pmqdator;		/* 0x7EC */
	uint16 pmqhst;			/* 0x7EE */
	uint16 pmqpath0;		/* 0x7F0 */
	uint16 pmqpath1;		/* 0x7F2 */
	uint16 pmqpath2;		/* 0x7F4 */
	uint16 pmqdath;			/* 0x7F6 */

	uint16 PAD[0x04];		/* 0x7F8 - 0x7FE */

	/* SHM */			/* 0x800 - 0xEFE */
	uint16	PAD[0x380];		/* 0x800 - 0xEFE */

	/* SB configuration registers:     0xF00 */
	sbconfig_t	sbconfig;	/* sb config regs occupy top 256 bytes */
} d11regs_t;

#define	PIHR_BASE	0x0400			/* byte address of packed IHR region */

/* biststatus */
#define	BT_DONE		((uint32)1 << 31)	/* bist done */
#define	BT_B2S		((uint32)1 << 30)	/* bist2 ram summary bit */

/* intstatus and intmask */
#define	I_PC		((uint32)1 << 10)	/* pci descriptor error */
#define	I_PD		((uint32)1 << 11)	/* pci data error */
#define	I_DE		((uint32)1 << 12)	/* descriptor protocol error */
#define	I_RU		((uint32)1 << 13)	/* receive descriptor underflow */
#define	I_RO		((uint32)1 << 14)	/* receive fifo overflow */
#define	I_XU		((uint32)1 << 15)	/* transmit fifo underflow */
#define	I_RI		((uint32)1 << 16)	/* receive interrupt */
#define	I_XI		((uint32)1 << 24)	/* transmit interrupt */