cpb8548drv.h

MPC8548上I2C控制器的初始化,读写单个字节,连续读写多个字节等函数.调试通过

/*=============================================================
*	Copyright (c) 2008~2010, CPIT. All Rights Reserved.
*
*	MODULE:  ecpb8548 驱动
*
*	FILENAME: cpb8548Drv.h
*
*	DESCRIPTION:ecpb 8548 驱动程序的宏定义，数据结构
*
*
*	HISTORY:
*
*	Date           CR No      Person        Description
*	----------  ------------  ------       -------------
*	                
*
=============================================================*/
#ifndef _CPB8548_DRV_H_
#define  _CPB8548_DRV_H_

#ifdef __cplusplus
extern "C" {
#endif


/*gpio reg define*/
#define M85XX_GPIOCR(base)                (CAST(VUINT32 *)((base) + 0xE0030))
#define M85XX_GPOUTDR(base)                (CAST(VUINT32 *)((base) + 0xE0040))
#define M85XX_GPINDR(base)                (CAST(VUINT32 *)((base) + 0xE0050))
#define M85XX_DEVDISR(base)            (CAST(VUINT32 *)((base) + 0xE0070))



#define TX2OUT (1<<25) /*Enables TSEC2_TX[7:0] for use as general-purpose output if the eTSEC2
                                 interface is disabled and eTSEC1 is not configured for 16-bit FIFO mode.*/                           
#define RX2IN (1<<24) /*Enables TSEC2_RX[7:0] for use as general-purpose input if the eTSEC2 
                                  interface is disabled and eTSEC1 is not configured for 16-bit FIFO mode.*/
#define PCIOUT (1<<17) /*Enables PCI2_AD[15:8] for use as general-purpose output. Note that 
                                   the PCI1 interface must be configured for 32-bit mode AND the PCI2
                                   interface must be disabled.*/                                  
#define PCIIN (1<<16) /*Enables PCI2_AD[7:0] for use as general-purpose input. Note that the
                                PCI1 interface must be configured for 32-bit mode AND the PCI2 interface must be disabled.*/ 

#define GPOUT (1<<9)

#define     ETSEC2_DISABLE    (1<<6) 
#define	PCI2_DISABLE  (1<<30)
#define	PCI1_DISABLE  (1<<31)


/*
FPGA1下载与8548相连引脚：

   INT_B  — GPIN_09

   DONE   — GPIN_08

   CS_B   — GPOUT_08

   CCLK   — GPOUT_10

   PROGRAM_B  — GPOUT_11

   DATA<7..0> — GPOUT_31..GPOUT_24

   FPGA2下载口与8548相连引脚：

   INT_B — GPIN_13

   DONE  — GPIN_12

   CS_B  — GPOUT_09

   CCLK  — GPOUT_15

   PROGRAM_B  — GPOUT_14

   DATA<7..0> — GPOUT_31..GPOUT_24
 */

#define FPGA1_PROG		(1<<20)
#define FPGA1_INIT		(1<<22)
#define FPGA1_CCLK		(1<<21)
#define FPGA1_CS		(1<<23)
/*#define FPGA1_BUSY*//*It's not need in this board*/
#define FPGA1_DONE		(1<<23)

#define FPGA2_PROG		(1<<17)
#define FPGA2_INIT		(1<<18)
#define FPGA2_CCLK		(1<<16)
#define FPGA2_CS		(1<<22)
/*#define FPGA2_BUSY*//*It's not need in this board*/
#define FPGA2_DONE		(1<<19)

#define FPGA_DATA_MASK	0x000000ff


#ifdef __cplusplus
}
#endif
#endif/*_ECPB8548_DRV_H_*/