swreg.c

VIA VT6524 8口网管交换机源码

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    swreg.c
 *
 * Purpose: Switch register hardware accessing functions
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 * Functions:
 *
 * Revision History:
 *
 */


#if !defined(__PLATFORM_H__)
#include "platform.h"
#endif
#if !defined(__SWREG_H__)
#include "swreg.h"
#endif




/*---------------------  Static Definitions -------------------------*/
#define MAX_LOOP_TIMEOUT        0xFFF

/*---------------------  Static Types  ------------------------------*/

/*---------------------  Static Macros  -----------------------------*/

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/

/*---------------------  Static Functions  --------------------------*/

/*---------------------  Export Variables  --------------------------*/
#ifdef __ASIC_VT6526
xdata BYTE x_byCpuPktData       _at_ 0xA000;
xdata BYTE x_byCpuRegData       _at_ 0xA101;    // For compatible with old decode circuit,
xdata BYTE x_byCpuRegAddrLow    _at_ 0xA202;    // use 0xA101 instead of 0xA001...
xdata BYTE x_byCpuRegAddrHi     _at_ 0xA303;
//xdata BYTE x_byModuleAddr       _at_ 0xD0FF;
#else   // __ASIC_VT6524 or __ASIC_VT6526D
xdata BYTE x_byCpuPktData       _at_ 0x0000;
xdata BYTE x_byCpuRegData       _at_ 0x0100;
xdata BYTE x_byCpuRegAddrLow    _at_ 0x0200;
xdata BYTE x_byCpuRegAddrHi     _at_ 0x0300;
#endif




// KEIL51 Directive: following set optimize level 4 and emphasis=size
#pragma ot(4, SIZE)

void SWREG_vReadB (UINT16 wAddr, PUINT8 pbyData) DIRECT_FUNTYPE_REENT
{
    // store CPU interrupt enabling status, then disable it
    PLATvCpuEnterCritical();

    // select address low
    x_byCpuRegAddrLow = wAddr & 0x00FF;
    // select address high
    x_byCpuRegAddrHi = wAddr >> 8;
    // Read cmd & data register
    *pbyData = x_byCpuRegData;

    // restore CPU interrupt status
    PLATvCpuExitCritical();
}


void SWREG_vWriteB (UINT16 wAddr, UINT8  byData) DIRECT_FUNTYPE_REENT
{
    // store CPU interrupt enabling status, then disable it
    PLATvCpuEnterCritical();

    // select address low
    x_byCpuRegAddrLow = wAddr & 0x00FF;
    // select address high
    x_byCpuRegAddrHi = wAddr >> 8;
    // write cmd & data register
    x_byCpuRegData = byData;

    // restore CPU interrupt status
    PLATvCpuExitCritical();
}

// KEIL51 Directive: following set optimize level 9 and emphasis=size
#pragma ot(9, SIZE)


void SWREG_vReadW (UINT16 wAddr, PUINT16 pwData) DIRECT_FUNTYPE_REENT
{
    SWREG_vReadB (wAddr,     (PBYTE)pwData + 1);
    SWREG_vReadB (wAddr + 1, (PBYTE)pwData);
}

void SWREG_vWriteW (UINT16 wAddr, UINT16 wData) DIRECT_FUNTYPE_REENT
{
    SWREG_vWriteB (wAddr + 1, (BYTE)(wData >> 8));
    SWREG_vWriteB (wAddr,     (BYTE)(wData & 0xFF));
}

void SWREG_vReadDW (UINT16 wAddr, PUINT32 pdwData) DIRECT_FUNTYPE_REENT
{
    SWREG_vReadB (wAddr,     (PBYTE)pdwData + 3);
    SWREG_vReadB (wAddr + 1, (PBYTE)pdwData + 2);
    SWREG_vReadB (wAddr + 2, (PBYTE)pdwData + 1);
    SWREG_vReadB (wAddr + 3, (PBYTE)pdwData);
}

void SWREG_vWriteDW (UINT16 wAddr, UINT32  dwData) DIRECT_FUNTYPE_REENT
{
    SWREG_vWriteB (wAddr + 3, (BYTE)((dwData >> 24) & 0xFF));
    SWREG_vWriteB (wAddr + 2, (BYTE)((dwData >> 16) & 0xFF));
    SWREG_vWriteB (wAddr + 1, (BYTE)((dwData >>  8) & 0xFF));
    SWREG_vWriteB (wAddr,     (BYTE)(dwData & 0xFF));
}



void SWREG_vBitsOn (UINT16 wAddr, UINT8 byBitPtn) DIRECT_FUNTYPE_REENT
{
    UINT8 byData;

    SWREG_vReadB(wAddr, &byData);
    SWREG_vWriteB(wAddr, (UINT8)(byData | byBitPtn));
}


void SWREG_vBitsOff (UINT16 wAddr, UINT8 byBitPtn) DIRECT_FUNTYPE_REENT
{
    UINT8 byData;

    SWREG_vReadB(wAddr, &byData);
    SWREG_vWriteB(wAddr, (UINT8)(byData & ~byBitPtn));
}


BOOL SWREG_bIfBitsOn (UINT16 wAddr, UINT8 byBitPtn) DIRECT_FUNTYPE_REENT
{
    UINT8 byOrgData;

    SWREG_vReadB(wAddr, &byOrgData);
    return ((byOrgData & byBitPtn) == byBitPtn);
}


BOOL SWREG_bIfBitsOff (UINT16 wAddr, UINT8 byBitPtn) DIRECT_FUNTYPE_REENT
{
    UINT8 byOrgData;

    SWREG_vReadB(wAddr, &byOrgData);
    return ((byOrgData & byBitPtn) == 0);
}


BOOL SWREG_bWaitStatus (UINT16 wAddr, UINT8 byStsBitPtn, BOOL bWaitCond) DIRECT_FUNTYPE_REENT
{
    BYTE   byStatus;
    UINT16 ui;



    // Loop to wait for specified register bit pattern
    for (ui = 0; ui < MAX_LOOP_TIMEOUT; ui++) {
        SWREG_vReadB(wAddr, &byStatus);    // read register status
        // Check if wait condition matched
        if ((bWaitCond == TRUE) && ((byStatus & byStsBitPtn) == byStsBitPtn))
            return TRUE;
        else if ((bWaitCond == FALSE) && ((byStatus & byStsBitPtn) == 0))
            return TRUE;
    }

    // timeout
    return FALSE;
}