swmii.h

VIA VT6524 8口网管交换机源码

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    swmii.h
 *
 * Purpose: Phy register hardware accessing functions
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 */


#ifndef __SWMII_H__
#define __SWMII_H__

#if !defined(__TTYPE_H__)
#include "ttype.h"
#endif




/*---------------------  Export Definitions  ------------------------*/
//
// Common registers in MII (offset unit is WORD)
//
#define MII_REG_BMCR        0x00        // 0x00 Basic Mode Control Register
#define MII_REG_BMSR        0x01        // 0x01 Basic Mode Status Register
#define MII_REG_PHYID1      0x02        // 0x02 PHY Identifier Register #1
#define MII_REG_PHYID2      0x03        // 0x03 PHY Identifier Register #2
#define MII_REG_ANAR        0x04        // 0x04 Auto-negotiation Advertisement Register
#define MII_REG_ANLPAR      0x05        // 0x05 Auto-negotiation Link Partner Ability Register
#define MII_REG_ANER        0x06        // 0x06 Auto-negotiation Expansion Register
#define MII_REG_NPTR        0x07        // 0x07 Next Page Transmit Register
#define MII_REG_LPNPR       0x08        // 0x08 Link Partner Next Page Register

// Giga phy registers
#define MII_REG_GBTCR       0x09        // 0x09 1000BASE-T Control Register
#define MII_REG_GBTSR       0x0A        // 0x0A 1000BASE-T Status Register

// Proprietary Registers
#define MII_REG_VIA_NWAYFRC     0x19    // 0x19 VIA Nway-Force Register
#define MII_REG_MARVELL_PSCR    0x10    // 0x10 Phy Specific Control Register
#define MII_REG_MARVELL_GBTCR   0x09    // 0x09 1000BASE-T Control Register
#define MII_REG_MARVELL_GBTSR   0x0A    // 0x0A 1000BASE-T Status Register
#define MII_REG_CICADA_ACSR     0x1C    // 0x1C CICADA ACSR Register


// Bits in the BMCR register
#define BMCR_RESET          0x8000
#define BMCR_LPBK           0x4000
#define BMCR_SPEED          0x2000
#define BMCR_AUTO           0x1000
#define BMCR_PD             0x0800
#define BMCR_ISO            0x0400
#define BMCR_REAUTO         0x0200
#define BMCR_FDX            0x0100
#define BMCR_COL            0x0080
#define BMCR_SPEED_GIGA     0x0040

// Bits in the BMSR register
#define BMSR_T4             0x8000
#define BMSR_TXFDX          0x4000
#define BMSR_TXHDX          0x2000
#define BMSR_10TFDX         0x1000
#define BMSR_10THDX         0x0800
#define BMSR_AUTOCM         0x0020
#define BMSR_RMTFL          0x0010
#define BMSR_CAUTO          0x0008
#define BMSR_LNK            0x0004
#define BMSR_JAB            0x0002
#define BMSR_EXTCAP         0x0001

// Bits in the ANAR register
#define ANAR_NP             0x8000
#define ANAR_ACK            0x4000
#define ANAR_RF             0x2000
#define ANAR_FLW            0x0C00
#define ANAR_T4             0x0200
#define ANAR_100TXF         0x0100
#define ANAR_100TXH         0x0080
#define ANAR_10TXF          0x0040
#define ANAR_10TXH          0x0020

// Bits in the ANLPAR register
#define ANLPAR_NP           0x8000
#define ANLPAR_ACK          0x4000
#define ANLPAR_RF           0x2000
#define ANLPAR_FLW          0x0400
#define ANLPAR_T4           0x0200
#define ANLPAR_100TXF       0x0100
#define ANLPAR_100TXH       0x0080
#define ANLPAR_10TXF        0x0040
#define ANLPAR_10TXH        0x0020

// Bits in the ANER register
#define ANER_LPANABLE       0x0001

// Bits in the PSCR register
#define PSCR_MDI0_MEGA      0x0010
#define PSCR_MDI1_MEGA      0x0020
#define PSCR_MDI0_GIGA      0x0020
#define PSCR_MDI1_GIGA      0x0040

// Bits in the GBTCR register
#define GBTCR_1000TF        0x0200
#define GBTCR_1000TH        0x0100


// Bits in proprietary registers
#define PTN_MARVELL_PSCR_MDI0_MEGA  0x0010
#define PTN_MARVELL_PSCR_MDI1_MEGA  0x0020
#define PTN_MARVELL_PSCR_MDI0_GIGA  0x0020
#define PTN_MARVELL_PSCR_MDI1_GIGA  0x0040
#define PTN_MARVELL_GBTCR_1000TF    0x0200
#define PTN_MARVELL_GBTCR_1000TH    0x0100

#define PTN_CICADA_ACSR_MODE_SEL    0x0004

#define PTN_VIA_NWAYFRC_ABL         0x0004
#define PTN_VIA_PHY_130             0x0008  // 0x03 bit3 0:130 1:233

// Company ID
#define CID_MARVELL                 0x0141
#define CID_CICADA                  0x000F
#define CID_VIA                     0x0101

// Module ID
// Note: The GIGA module we supported are listed here.
//       If not listed, it will be recognized as MEGA module.
#define MID_MARVELL_88E1000         0x0C50
#define MID_CICADA_CIS8201          0xC410
#define MID_VIA_VT6108              0x8F90


// Phy module code
#define PHY_STANDARD                0x00
#define PHY_MARVELL_MEGA            0x10
#define PHY_MARVELL_GIGA            0x11
#define PHY_CICADA_GIGA             0x21
#define PHY_VIA_MEGA                0x30

// Port ability related pattern
#define PTN_PHY_ANAR_ABL_MEGA       (ANAR_100TXF | ANAR_100TXH | ANAR_10TXF | ANAR_10TXH)
#define PTN_PHY_GBTCR_ABL_GIGA      (GBTCR_1000TF | GBTCR_1000TH)

/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Export Functions  --------------------------*/
BOOL SWMII_bReadW (BYTE byPortId, BYTE byAddr, PUINT16 pwData) DIRECT_FUNTYPE_REENT;
BOOL SWMII_bWriteW(BYTE byPortId, BYTE byAddr, UINT16 wData)   DIRECT_FUNTYPE_REENT;

BOOL SWMII_bRegBitsOn (BYTE byPortId, BYTE byAddr, UINT16 wBitPtn)   DIRECT_FUNTYPE_REENT;
BOOL SWMII_bRegBitsOff(BYTE byPortId, BYTE byAddr, UINT16 wBitPtn)   DIRECT_FUNTYPE_REENT;

BOOL SWMII_bIsRegBitsOn (BYTE byPortId, BYTE byAddr, UINT16 wBitPtn) DIRECT_FUNTYPE_REENT;
BOOL SWMII_bIsRegBitsOff(BYTE byPortId, BYTE byAddr, UINT16 wBitPtn) DIRECT_FUNTYPE_REENT;

void SWMII_vSetAutoPollOn (void) DIRECT_FUNTYPE_REENT;
void SWMII_vSetAutoPollOff(void) DIRECT_FUNTYPE_REENT;

#ifdef __ASIC_VT6526
BYTE SWMII_byGetPhyType(BYTE byPortId) DIRECT_FUNTYPE_REENT;
#endif




#endif /* __SWMII_H__ */