swport.c

VIA VT6524 8口网管交换机源码

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    swport.c
 *
 * Purpose: Port configuration and status hardware accessing functions
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 * Functions:
 *
 * Revision History:
 *
 */


#if !defined(__SWITCH_H__)
#include "switch.h"
#endif
#if !defined(__SWMII_H__)
#include "swmii.h"
#endif
#if !defined(__PLATFORM_H__)
#include "platform.h"
#endif
#if !defined(__SWMSG_H__)
#include "swmsg.h"
#endif
#if !defined(__SWPORT_H__)
#include "swport.h"
#endif




/*---------------------  Static Definitions  ------------------------*/

// for switch register PHY_PORT_ABL
#define PTN_PHY_PORT_ABL_ENABLE         0x03
#define PTN_PHY_PORT_ABL_HALF_DPX       0x04
#define PTN_PHY_PORT_ABL_SPD10          0x20
#define PTN_PHY_PORT_ABL_SPD1000        0x40


#ifdef __ASIC_VT6526

// for switch register PHY_TBI_ABL
#define PTN_PHY_TBI_ABL_NWAY            0x01
#define PTN_PHY_TBI_ABL_FLWCTL          0x0C
#define PTN_PHY_MODULE_POWER_DOWN       0x0800


// for N-way force only
static DIRECT_MEMTYPE_CODE UINT16 s_awSpdDpxPtn[] = {
    ANAR_100TXF,
    ANAR_100TXH,
    ANAR_10TXF,
    ANAR_10TXH,
    GBTCR_1000TF,
    GBTCR_1000TH,
};

// for force mode
static DIRECT_MEMTYPE_CODE UINT16 s_awFrcSpdDpxMiiVal[] = {
    (BMCR_SPEED_GIGA | BMCR_SPEED | BMCR_FDX | BMCR_AUTO),  // bits
    (BMCR_SPEED | BMCR_FDX),
    BMCR_SPEED,
    BMCR_FDX,
    0,
    (BMCR_SPEED_GIGA | BMCR_FDX),
    BMCR_SPEED_GIGA
};

static DIRECT_MEMTYPE_CODE UINT8 s_abyFrcSpdDpxBitOn[] = {
    0,
    PTN_PHY_PORT_ABL_HALF_DPX,
    PTN_PHY_PORT_ABL_SPD10,
    (PTN_PHY_PORT_ABL_HALF_DPX | PTN_PHY_PORT_ABL_SPD10),
    PTN_PHY_PORT_ABL_SPD1000,
    (PTN_PHY_PORT_ABL_HALF_DPX | PTN_PHY_PORT_ABL_SPD1000)
};

static DIRECT_MEMTYPE_CODE UINT8 s_abyFrcSpdDpxBitOff[] = {
    (PTN_PHY_PORT_ABL_HALF_DPX | PTN_PHY_PORT_ABL_SPD10 | PTN_PHY_PORT_ABL_SPD1000),
    (PTN_PHY_PORT_ABL_SPD10 | PTN_PHY_PORT_ABL_SPD1000),
    (PTN_PHY_PORT_ABL_HALF_DPX | PTN_PHY_PORT_ABL_SPD1000),
    PTN_PHY_PORT_ABL_SPD1000,
    (PTN_PHY_PORT_ABL_HALF_DPX | PTN_PHY_PORT_ABL_SPD10),
    PTN_PHY_PORT_ABL_SPD10
};

#else // VT6524

// for auto and N-way force mode
static DIRECT_MEMTYPE_CODE UINT16 s_awSpdDpxPtn[] = {
    PTN_PHY_ANAR_ABL_MEGA,  // auto
    ANAR_100TXF,            // 100F
    ANAR_100TXH,            // 100H
    ANAR_10TXF,             // 10F
    ANAR_10TXH              // 10H
};

// for force mode
static DIRECT_MEMTYPE_CODE UINT16 s_awFrcSpdDpxMiiVal[] = {
    (BMCR_SPEED | BMCR_FDX | BMCR_AUTO),    // bits off
    (BMCR_SPEED | BMCR_FDX),    // 100F
    BMCR_SPEED,                 // 100H
    BMCR_FDX,                   // 10F
    0,                          // 10H
};

static DIRECT_MEMTYPE_CODE UINT8 s_abyFrcSpdDpxBitOn[] = {
    0,                                                      // 100F
    PTN_PHY_PORT_ABL_HALF_DPX,                              // 100H
    PTN_PHY_PORT_ABL_SPD10,                                 // 10F
    (PTN_PHY_PORT_ABL_HALF_DPX | PTN_PHY_PORT_ABL_SPD10)    // 10H
};

static DIRECT_MEMTYPE_CODE UINT8 s_abyFrcSpdDpxBitOff[] = {
    (PTN_PHY_PORT_ABL_HALF_DPX | PTN_PHY_PORT_ABL_SPD10),   // 100F
    (PTN_PHY_PORT_ABL_SPD10),                               // 100H
    (PTN_PHY_PORT_ABL_HALF_DPX),                            // 10F
    0                                                       // 10H
};

#endif

/*---------------------  Static Types  ------------------------------*/

/*---------------------  Static Macros  -----------------------------*/

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/

/*---------------------  Static Functions  --------------------------*/

/*---------------------  Export Variables  --------------------------*/




#ifdef __ASIC_VT6526


BOOL SWPORT_bIfTbiPort(UINT8 byPortId) DIRECT_FUNTYPE_REENT
{
    // Get port strapping config
    if ((SWITCH_PORT_NUM > byPortId) && (byPortId >= SWITCH_MEGA_PORT_NUM))
        return (SWREG_vIsSpecBitOff(GLOBAL_CHIP_CFG, 10 + (byPortId - SWITCH_MEGA_PORT_NUM)));
    else
        return FALSE;           // Mega ports must not be TBI mode
}


BOOL SWPORT_bGetPortEn(BYTE byPortId) DIRECT_FUNTYPE_REENT
{
    if (SWPORT_bIfTbiPort(byPortId)) {
        // Get port enable
        if( SWREG_vIsSpecBitOn(PHY_PORT_NWAY_EN_MASK, byPortId * 2) &&
            SWREG_vIsSpecBitOn(PHY_PORT_NWAY_EN_MASK, byPortId * 2 + 1) )
            return TRUE;
        else
            return FALSE;
    }
    else {
        return SWMII_bIsRegBitsOff(byPortId, MII_REG_BMCR, BMCR_PD);
    }
}


void SWPORT_vSetPortEn(UINT8 byPortId, BOOL bPortEbl) DIRECT_FUNTYPE_REENT
{
    if (SWPORT_bIfTbiPort(byPortId)) {
        // Set port enable
        if (bPortEbl) {
            // Enable Nway mask
            SWREG_vSpecBitOn(PHY_PORT_NWAY_EN_MASK, byPortId * 2);
            SWREG_vSpecBitOn(PHY_PORT_NWAY_EN_MASK, byPortId * 2 + 1);
            // If port link up, open port I/O
            if (SWREG_vIsSpecBitOn(PHY_LINK_STATUS, byPortId))
                SWREG_vBitsOn ( PHY_PORT_ABL_BASE + byPortId, PTN_PHY_PORT_ABL_ENABLE );
        }
        else {
            // Disable Nway mask
            SWREG_vSpecBitOff(PHY_PORT_NWAY_EN_MASK, byPortId * 2);
            SWREG_vSpecBitOff(PHY_PORT_NWAY_EN_MASK, byPortId * 2 + 1);
            // Disable MAC I/O
            SWREG_vBitsOff( PHY_PORT_ABL_BASE + byPortId, PTN_PHY_PORT_ABL_ENABLE );
        }
    }
    else {
        // Set port enable
        if (bPortEbl)
            SWMII_bRegBitsOff(byPortId, MII_REG_BMCR, BMCR_PD);
        else
            SWMII_bRegBitsOn(byPortId, MII_REG_BMCR, BMCR_PD);
    }
}


UINT8 SWPORT_byGetSpdDpx (UINT8 byPortId) DIRECT_FUNTYPE_REENT
{
	BYTE byData;
	
	
	SWREG_vReadB(PHY_PORT_ABL_BASE+byPortId, &byData);
	if (byData & PTN_PHY_PORT_ABL_HALF_DPX)	{
		if (byData & PTN_PHY_PORT_ABL_SPD1000)
            return PORT_SPDPX_1000M_HALF;
		else if (byData & PTN_PHY_PORT_ABL_SPD10)
            return PORT_SPDPX_10M_HALF;
		else
            return PORT_SPDPX_100M_HALF;
	}
	else {
		if (byData & PTN_PHY_PORT_ABL_SPD1000)
            return PORT_SPDPX_1000M_FULL;
		else if (byData & PTN_PHY_PORT_ABL_SPD10)
            return PORT_SPDPX_10M_FULL;
        else
            return PORT_SPDPX_100M_FULL;
	}
}


BYTE SWPORT_bySetSpdDpx(UINT8 byPortId, BOOL bAuto, UINT8 byPortAbl) DIRECT_FUNTYPE_REENT
{
    BOOL    bIfTBIPort = SWPORT_bIfTbiPort(byPortId);