switch.h

VIA VT6524 8口网管交换机源码

#define FWD_AUTO_AGE                FWD_BASE_ADDR + 0x03
#define FWD_AGE_CYC_TIME            FWD_BASE_ADDR + 0x04
#define FWD_INTER_AGE_TIME          FWD_BASE_ADDR + 0x05
#define FWD_AGE_INDEX               FWD_BASE_ADDR + 0x06
#define FWD_AGE_STATUS              FWD_BASE_ADDR + 0x08
#define FWD_CPU_FWD_CFG             FWD_BASE_ADDR + 0x09
#define FWD_IP_CAPTURE_CFG          FWD_BASE_ADDR + 0x0A
#define FWD_IP_MCAST_CFG            FWD_BASE_ADDR + 0x0C
#define FWD_VLAN_CFG                FWD_BASE_ADDR + 0x0D
#define FWD_PROTO_VLAN_EN           FWD_BASE_ADDR + 0x0E
#define FWD_CPU_PM                  FWD_BASE_ADDR + 0x0F

#define FWD_CPU_VLAN_TAG_RULE       FWD_BASE_ADDR + 0x13
#define FWD_FLOOD_DPM               FWD_BASE_ADDR + 0x17
#define FWD_IP_FLOOD_DPM            FWD_BASE_ADDR + 0x1B
#define FWD_HASH_CONFLICT_CNT       FWD_BASE_ADDR + 0x1F

#define FWD_PORT_SNIFF_CFG          FWD_BASE_ADDR + 0x21
#define FWD_PORT_SNIFF_MODE         FWD_BASE_ADDR + 0x25
#define FWD_FLOW_SNIFF_CFG          FWD_BASE_ADDR + 0x26
#define FWD_HASH_KEY                FWD_BASE_ADDR + 0x28

#define FWD_HASH_CAL_STATUS         FWD_BASE_ADDR + 0x30
#define FWD_HASH_RESULT             FWD_BASE_ADDR + 0x31
#define FWD_PRIORITY_MAP            FWD_BASE_ADDR + 0x33
#define FWD_DROP_ON                 FWD_BASE_ADDR + 0x34
#define FWD_SECURITY_CFG            FWD_BASE_ADDR + 0x38
#define FWD_MISC_CFG                FWD_BASE_ADDR + 0x3C
#define FWD_TICKET_ALG              FWD_BASE_ADDR + 0x3D
#define FWD_TRUNK_CFG_BASE          FWD_BASE_ADDR + 0x3E

#define FWD_LOOKUP_CFG0             FWD_BASE_ADDR + 0x58
#define FWD_LOOKUP_CFG1             FWD_BASE_ADDR + 0x5A
#define FWD_LOOKUP_CFG2             FWD_BASE_ADDR + 0x5C
#define FWD_LOOKUP_CFG3             FWD_BASE_ADDR + 0x5E

#define FWD_ETHERTYPE_VALID         FWD_BASE_ADDR + 0x60
#define FWD_SAPS_VALID              FWD_BASE_ADDR + 0x62
#define FWD_DSAP_LSB_MASK           FWD_BASE_ADDR + 0x63
#define FWD_SSAP_LSB_MASK           FWD_BASE_ADDR + 0x64
#define FWD_FWD_ARP_TO_CPU          FWD_BASE_ADDR + 0x65
#define FWD_BCST_DPM                FWD_BASE_ADDR + 0x66
#define FWD_STP_STATE_BASE          FWD_BASE_ADDR + 0x6A

#define FWD_SCAN_MACTBL_MODE        FWD_BASE_ADDR + 0x84
#define FWD_MOVE_FROM_PORT_ID       FWD_BASE_ADDR + 0x85
#define FWD_MOVE_TO_PORT_ID         FWD_BASE_ADDR + 0x86
#define FWD_PVID_BASE               FWD_BASE_ADDR + 0x87

#define FWD_ETHERTYPE14             FWD_BASE_ADDR + 0xA2
#define FWD_ETHERTYPE15             FWD_BASE_ADDR + 0xA4
#define FWD_SAPS7                   FWD_BASE_ADDR + 0xA6
#define FWD_RMON_SAMPLE_EN          FWD_BASE_ADDR + 0xA8
#define FWD_RMON_SCPC               FWD_BASE_ADDR + 0xA9
#define FWD_RMON_PORT_ID            FWD_BASE_ADDR + 0xAC
#define FWD_RMON_CDC                FWD_BASE_ADDR + 0xAD

#define FWD_INGRESS_FILTR_BASE      FWD_BASE_ADDR + 0xB0

#define FWD_PVID_BASE_11_8          FWD_BASE_ADDR + 0xCA    // for 3221 only
#define FWD_OPTIONAL_CFG            FWD_BASE_ADDR + 0xE4    // for 3221 only


// PHY Control
#define PHY_BASE_ADDR               0x0400

#define PHY_CMD_PORTID              PHY_BASE_ADDR + 0x00
#define PHY_REG_ADDR                PHY_BASE_ADDR + 0x01
#define PHY_DATA                    PHY_BASE_ADDR + 0x02
#define PHY_CMD                     PHY_BASE_ADDR + 0x04
#define PHY_STATUS                  PHY_BASE_ADDR + 0x05
#define PHY_LINK_STATUS_CHANGE      PHY_BASE_ADDR + 0x06
#define PHY_LINK_STATUS             PHY_BASE_ADDR + 0x0A
#define PHY_DBG_EN                  PHY_BASE_ADDR + 0x0E
#define PHY_TRIG_STEP_POLL          PHY_BASE_ADDR + 0x0F

#define PHY_POLLING_STATE           PHY_BASE_ADDR + 0x10
#define PHY_FLOW_CTRL_ABL           PHY_BASE_ADDR + 0x11
#define PHY_BACK_PRESSURE_DIS       PHY_BASE_ADDR + 0x18
#define PHY_ADDR_BASE               PHY_BASE_ADDR + 0x1C

#define PHY_INVALID_NUM_G1          PHY_BASE_ADDR + 0x36
#define PHY_INVALID_NUM_G2          PHY_BASE_ADDR + 0x37
#define PHY_TBI_ABL_G1              PHY_BASE_ADDR + 0x38
#define PHY_TBI_ABL_G2              PHY_BASE_ADDR + 0x39
#define PHY_TBI_STATUS_G1           PHY_BASE_ADDR + 0x3A
#define PHY_TBI_STATUS_G2           PHY_BASE_ADDR + 0x3B
#define PHY_TBI_RST_EN_G1           PHY_BASE_ADDR + 0x3C
#define PHY_TBI_RST_EN_G2           PHY_BASE_ADDR + 0x3D

#define PHY_PORT_ABL_BASE           PHY_BASE_ADDR + 0x40

#define PHY_PORT_ABL_G1             PHY_BASE_ADDR + 0x58
#define PHY_PORT_ABL_G2             PHY_BASE_ADDR + 0x59
#define PHY_PORT_NWAY_EN_MASK       PHY_BASE_ADDR + 0x5A
#define PHY_GIGA_PORT_NWAY_EN_MASK  PHY_BASE_ADDR + 0x60
#define PHY_GMII_MII_AUTOPOLL_CFG   PHY_BASE_ADDR + 0x61


// EEPROM Control
#define EEPROM_BASE_ADDR            0x0500

#define EEPROM_ADDR                 EEPROM_BASE_ADDR + 0x00
#define EEPROM_DATA                 EEPROM_BASE_ADDR + 0x01
#define EEPROM_DEV_ADDR             EEPROM_BASE_ADDR + 0x02
#define EEPROM_STATUS               EEPROM_BASE_ADDR + 0x03


// CPU Interface Control
#define CPU_BASE_ADDR               0x0600

#define CPU_IRQ_STATUS              CPU_BASE_ADDR + 0x00
#define CPU_IRQ_MASK                CPU_BASE_ADDR + 0x01
#define CPU_SRAM_ADDR               CPU_BASE_ADDR + 0x02
#define CPU_SRAM_DATA               CPU_BASE_ADDR + 0x04

#define CPU_SRAM_CMD                CPU_BASE_ADDR + 0x14
#define CPU_SRAM_STATUS             CPU_BASE_ADDR + 0x15
#define CPU_INTRQ_MODE              CPU_BASE_ADDR + 0x16
#define CPU_WR_PKT_CMD              CPU_BASE_ADDR + 0x17
#define CPU_PKT_ABORT               CPU_BASE_ADDR + 0x18
#define CPU_SWITCH_MAC              CPU_BASE_ADDR + 0x19
#define CPU_NWAIT_CONFIG            CPU_BASE_ADDR + 0x1F

#define CPU_DMA_STATUS              CPU_BASE_ADDR + 0x21
#define CPU_DMA_START_ADDR          CPU_BASE_ADDR + 0x22
#define CPU_DMA_TRANS_CNT           CPU_BASE_ADDR + 0x24
#define CPU_DMA_TYPE                CPU_BASE_ADDR + 0x26
#define CPU_DMA_CH_RDY              CPU_BASE_ADDR + 0x27
#define CPU_DMA_TRANS_DONE          CPU_BASE_ADDR + 0x28
#define CPU_DMA_MODE                CPU_BASE_ADDR + 0x29
#define CPU_DMA_RD_MEM_STS          CPU_BASE_ADDR + 0x2A
#define CPU_DMA_MEM_ABORT           CPU_BASE_ADDR + 0x2B
#define CPU_DMA_DEMAND_CNT          CPU_BASE_ADDR + 0x2C
#define CPU_DMA_WAIT_CNT            CPU_BASE_ADDR + 0x2E
#define CPU_RMON_IRQ_STATUS         CPU_BASE_ADDR + 0x30
#define CPU_RMON_IRQ_MASK           CPU_BASE_ADDR + 0x34
#define CPU_RMON_ERR_DATA           CPU_BASE_ADDR + 0x38
#define CPU_ENDIAN                  CPU_BASE_ADDR + 0x3F


// BCAST Strom Filtering Control
#define BSF_BASE_ADDR               0x0700

#define BSF_BCAST_SEG_CNT           BSF_BASE_ADDR + 0x00
#define BSF_XON_THRED               BSF_BASE_ADDR + 0x02
#define BSF_XOFF_THRED              BSF_BASE_ADDR + 0x04
#define BSF_XOFF                    BSF_BASE_ADDR + 0x06


// SRAM Control
#define SRAM_BASE_ADDR              0x0800

#define SRAM_BIST_STATUS            SRAM_BASE_ADDR + 0x00


// MAC IO Control
#define MACIO_BASE_ADDR             0x1000
#define MACIO_PORT_OFFSET           0x100

#define MACIO_DEQUE_HOLD            MACIO_BASE_ADDR + 0x00
#define MACIO_IN_PRIOR_OVERWRITE    MACIO_BASE_ADDR + 0x01
#define MACIO_IO_REDNT_REG          MACIO_BASE_ADDR + 0x02
#define MACIO_FREE_BUF_ADDR1        MACIO_BASE_ADDR + 0x04
#define MACIO_FREE_BUF_ADDR2        MACIO_BASE_ADDR + 0x06
#define MACIO_FREE_BUF_ADDR3        MACIO_BASE_ADDR + 0x08
#define MACIO_FREE_BUF_ADDR4        MACIO_BASE_ADDR + 0x0A
#define MACIO_DEQUE_BUF_ADDR1       MACIO_BASE_ADDR + 0x0C
#define MACIO_DEQUE_BUF_SEG_ADDR1   MACIO_BASE_ADDR + 0x0E
#define MACIO_DEQUE_BUF_ADDR2       MACIO_BASE_ADDR + 0x10
#define MACIO_DEQUE_BUF_SEG_ADDR2   MACIO_BASE_ADDR + 0x12
#define MACIO_INPUT_CTRL_STATE      MACIO_BASE_ADDR + 0x14
#define MACIO_OUTPUT_CTRL_STATE     MACIO_BASE_ADDR + 0x15

// for VT3221 only
#define MACIO_RX_PKT_CNT            MACIO_BASE_ADDR + 0x16
#define MACIO_TX_PKT_CNT            MACIO_BASE_ADDR + 0x18
#define MACIO_ACCOUNT_OPT           MACIO_BASE_ADDR + 0x20


// CPU IO Control
#define CPUIO_BASE_ADDR             0x2A00

#define CPUIO_CFG                   CPUIO_BASE_ADDR + 0x00
#define CPUIO_RD_PKT_RDY            CPUIO_BASE_ADDR + 0x01
#define CPUIO_RD_PKT_STATUS         CPUIO_BASE_ADDR + 0x02
#define CPUIO_RD_PKT_ATTRIB         CPUIO_BASE_ADDR + 0x03
#define CPUIO_RD_PKT_BYTE_CNT       CPUIO_BASE_ADDR + 0x04
#define CPUIO_RD_PKT_VLAN_TAG       CPUIO_BASE_ADDR + 0x06
#define CPUIO_DEQUE_ADDR0           CPUIO_BASE_ADDR + 0x08
#define CPUIO_DEQUE_SEG_ADDR0       CPUIO_BASE_ADDR + 0x0A
#define CPUIO_DEQUE_ADDR1           CPUIO_BASE_ADDR + 0x0C
#define CPUIO_DEQUE_SEG_ADDR1       CPUIO_BASE_ADDR + 0x0E
#define CPUIO_WR_PKT_RDY            CPUIO_BASE_ADDR + 0x12
#define CPUIO_WR_PKT_STATUS         CPUIO_BASE_ADDR + 0x13
#define CPUIO_WR_PKT_VLAN_TAG       CPUIO_BASE_ADDR + 0x14
#define CPUIO_WR_DMAC_CFG           CPUIO_BASE_ADDR + 0x16
#define CPUIO_FREE_BUF_ADDR0        CPUIO_BASE_ADDR + 0x18
#define CPUIO_FREE_BUF_ADDR1        CPUIO_BASE_ADDR + 0x1A
#define CPUIO_FREE_BUF_ADDR2        CPUIO_BASE_ADDR + 0x1C
#define CPUIO_FREE_BUF_ADDR3        CPUIO_BASE_ADDR + 0x1E

// for VT3221 only
#define CPUIO_RX_PKT_CNT            CPUIO_BASE_ADDR + 0x20
#define CPUIO_TX_PKT_CNT            CPUIO_BASE_ADDR + 0x22
#define CPUIO_ACCOUNT_OPT           CPUIO_BASE_ADDR + 0x24


// Global Configuration II (VT3221 only)
#define GLOBAL2_BASE_ADDR           0x2B00

#define GLOBAL2_PWRUPCTRL_CMD0      GLOBAL2_BASE_ADDR + 0x01
#define GLOBAL2_PWRUPCTRL_CMD1      GLOBAL2_BASE_ADDR + 0x02

/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Export Functions  --------------------------*/




#endif /* __SWITCH_H__ */