switch.h

VIA VT6524 8口网管交换机源码

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    switch.h
 *
 * Purpose: Switch hardware feature and register address definition
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 */


#ifndef __SWITCH_H__
#define __SWITCH_H__




/*---------------------  Export Definitions  ------------------------*/

//--------------------------------------
// Definition for Switch Ports
//--------------------------------------

#ifdef __ASIC_VT6524
    #define SWITCH_PORT_NUM             8
    #define SWITCH_MEGA_PORT_NUM        8
#else   // __ASIC_VT6526 or __ASIC_VT6526D
    #define SWITCH_PORT_NUM             26
    #define SWITCH_MEGA_PORT_NUM        24
    #define SWITCH_GIGA_PORT_NUM        2
    #define SWITCH_GIGA_PORT_ID_BASE    SWITCH_MEGA_PORT_NUM
#endif

#define SWITCH_TRUNKABLE_PORT_NUM   SWITCH_MEGA_PORT_NUM
#define SWITCH_TRUNK_GRP_NUM        7
#define SWITCH_VLAN_GRP_NUM         SWITCH_PORT_NUM

// Bit pattern for port mask
#define PTN_BIT_MASK_ALL_PORT       0x03FFFFFFUL
#define PTN_BIT_MASK_CPU_PORT       0x04000000UL


//--------------------------------------
// Definition for I2C EEPROM
//--------------------------------------

// Define eeprom device id for user configuration
#ifdef __ASIC_VT6526
    #define EEP_DEV_ID              4   // addr 1024
#else   // __ASIC_VT6524 or __ASIC_VT6526D
    #define EEP_DEV_ID              0
#endif


//--------------------------------------
// Definition for SRAM: Packet Data Memory
//--------------------------------------

#ifdef __ASIC_VT6526
    #define SRAM_PKT_BLK0_BASE_ADDR     0x0000
    #define SRAM_PKT_BLK1_BASE_ADDR     0x4000
    #define SRAM_PKT_BLOCK_SIZE         0x3000      // 0x3000 = 12K entry = 3M bit / 128 bit / 2
#else
    #define SRAM_PKT_BLK_BASE_ADDR      0x0000
    #define SRAM_PKT_BLOCK_SIZE         0x4000
#endif

#define SRAM_PKT_SLOT_SIZE              16


//--------------------------------------
// Definition for SRAM: Control Data Memory
//--------------------------------------

// Switch hardware related constants
#define SRAM_CTRL_BLK_BASE_ADDR         0x8000
#define SRAM_CTRL_BLOCK_SIZE            0x3C00      // 0x3C00 = 15K = 14K + 0.5K + 0.5K
                                                    // 14K  : Address and VLAN table
                                                    // 0.5K : IP Multicast table
                                                    // 0.5K : Protocol-based VLAN table

#define SRAM_CTRL_SLOT_SIZE             8


//--------------------------------------
// Definition for Switch Registers
//--------------------------------------

// 0000H Global Configuration
// 0100H Queue Control
// 0200H Buffer Control
// 0300H Forwarding Table Configuration
// 0400H PHY Control
// 0500H EEPROM Control
// 0600H CPU Interface Control
// 0700H Broadcast Strom Filtering Control
// 0800H SRAM Control
// 1000H MAC IO Control
// 2A00H CPU IO Control
// 2B00H Global Configuration II (VT3221 only)


// Global Configuration
#define GLOBAL_BASE_ADDR            0x0000

#define GLOBAL_CHIP_CFG             GLOBAL_BASE_ADDR + 0x00
#define GLOBAL_FUNC_CFG             GLOBAL_BASE_ADDR + 0x02
#define GLOBAL_PAD_CFG              GLOBAL_BASE_ADDR + 0x04
#define GLOBAL_REVISION_ID          GLOBAL_BASE_ADDR + 0x08
#define GLOBAL_LED_OUT_EN           GLOBAL_BASE_ADDR + 0x09
#define GLOBAL_LED_GRP_EN           GLOBAL_BASE_ADDR + 0x0A
#define GLOBAL_PULSE_STRETCH        GLOBAL_BASE_ADDR + 0x0D
#define GLOBAL_UPDATE_TIME          GLOBAL_BASE_ADDR + 0x0E
#define GLOBAL_BW_UTIL              GLOBAL_BASE_ADDR + 0x0F

#define GLOBAL_PORT_IORATE_BASE     GLOBAL_BASE_ADDR + 0x10

#define GLOBAL_PREAM_CFG            GLOBAL_BASE_ADDR + 0x2A
#define GLOBAL_IFG_CFG              GLOBAL_BASE_ADDR + 0x2B
#define GLOBAL_BKOFF_CFG            GLOBAL_BASE_ADDR + 0x2C
#define GLOBAL_BP_CRS_CFG           GLOBAL_BASE_ADDR + 0x2D
#define GLOBAL_REAUTO_EN            GLOBAL_BASE_ADDR + 0x2E
#define GLOBAL_RST_TMAC             GLOBAL_BASE_ADDR + 0x2F

#define GLOBAL_PREAM_CFG_G1         GLOBAL_BASE_ADDR + 0x30
#define GLOBAL_IFG_CFG_G1           GLOBAL_BASE_ADDR + 0x31
#define GLOBAL_BKOFF_CFG_G1         GLOBAL_BASE_ADDR + 0x32
#define GLOBAL_BP_CRS_CFG_G1        GLOBAL_BASE_ADDR + 0x33
#define GLOBAL_REAUTO_EN_G1         GLOBAL_BASE_ADDR + 0x34
#define GLOBAL_RST_TMAC_G1          GLOBAL_BASE_ADDR + 0x35
#define GLOBAL_FRAME_BT_EN_G1       GLOBAL_BASE_ADDR + 0x36
#define GLOBAL_PREAM_CFG_G2         GLOBAL_BASE_ADDR + 0x37
#define GLOBAL_IFG_CFG_G2           GLOBAL_BASE_ADDR + 0x38
#define GLOBAL_BKOFF_CFG_G2         GLOBAL_BASE_ADDR + 0x39
#define GLOBAL_BP_CRS_CFG_G2        GLOBAL_BASE_ADDR + 0x3A
#define GLOBAL_REAUTO_EN_G2         GLOBAL_BASE_ADDR + 0x3B
#define GLOBAL_RST_TMAC_G2          GLOBAL_BASE_ADDR + 0x3C
#define GLOBAL_FRAME_BT_EN_G2       GLOBAL_BASE_ADDR + 0x3D
#define GLOBAL_MAX_PKT_LEN          GLOBAL_BASE_ADDR + 0x3E

#define GLOBAL_DBG_GROUP_ID         GLOBAL_BASE_ADDR + 0x40
#define GLOBAL_SMII_SYNC_SEL        GLOBAL_BASE_ADDR + 0x41
#define GLOBAL_IFG_COMP_RANGE       GLOBAL_BASE_ADDR + 0x46
#define GLOBAL_CPU_SOFT_RESET       GLOBAL_BASE_ADDR + 0x50


// Queue Control
#define QUE_BASE_ADDR               0x0100

#define QUE_SYS_XON_THR             QUE_BASE_ADDR + 0x00
#define QUE_SYS_XOFF_THR            QUE_BASE_ADDR + 0x02
#define QUE_ALL_XOFF_THR            QUE_BASE_ADDR + 0x04
#define QUE_CONG_ON_BELOW_10M       QUE_BASE_ADDR + 0x06
#define QUE_CONG_ON_10M             QUE_BASE_ADDR + 0x07
#define QUE_CONG_ON_100M            QUE_BASE_ADDR + 0x08
#define QUE_CONG_ON_1000M           QUE_BASE_ADDR + 0x09
#define QUE_CONG_ON_CPU             QUE_BASE_ADDR + 0x0A
#define QUE_CONG_OFF_BELOW_10M      QUE_BASE_ADDR + 0x0B
#define QUE_CONG_OFF_10M            QUE_BASE_ADDR + 0x0C
#define QUE_CONG_OFF_100M           QUE_BASE_ADDR + 0x0D
#define QUE_CONG_OFF_1000M          QUE_BASE_ADDR + 0x0E
#define QUE_CONG_OFF_CPU            QUE_BASE_ADDR + 0x0F

#define QUE_SYS_XOFF_WIN            QUE_BASE_ADDR + 0x10
#define QUE_CPU_CONG_MODE           QUE_BASE_ADDR + 0x11
#define QUE_OUT_CONG_WIN            QUE_BASE_ADDR + 0x12
#define QUE_IN_XOFF_WIN             QUE_BASE_ADDR + 0x19
#define QUE_ID                      QUE_BASE_ADDR + 0x1D
#define QUE_CONG_MAKER              QUE_BASE_ADDR + 0x1E
#define QUE_SEG_LEN                 QUE_BASE_ADDR + 0x22
#define QUE_HEAD                    QUE_BASE_ADDR + 0x24
#define QUE_TAIL                    QUE_BASE_ADDR + 0x26
#define QUE_HEAD_ARR_TIME           QUE_BASE_ADDR + 0x28
#define QUE_PKT_STAMP_TIMER         QUE_BASE_ADDR + 0x2A
#define QUE_SCHE_SEL                QUE_BASE_ADDR + 0x2C
#define QUE_DELAY_BOUND_EN          QUE_BASE_ADDR + 0x2D
#define QUE_DELAY_BOUND             QUE_BASE_ADDR + 0x2E
#define QUE_TRANS_DELAY_SEL         QUE_BASE_ADDR + 0x2F

#define QUE_EGRESS_RATE_BASE        QUE_BASE_ADDR + 0x30
#define QUE_INGRESS_RATE_BASE       QUE_BASE_ADDR + 0x60

#define QUE_INGRESS_XOFF_WIN        QUE_BASE_ADDR + 0x90
#define QUE_STEP_DEQUE_EN           QUE_BASE_ADDR + 0x93


// Buffer Control
#define BUF_BASE_ADDR               0x0200

#define BUF_FREE_MEM_CNT            BUF_BASE_ADDR + 0x00
#define BUF_MASK_ID                 BUF_BASE_ADDR + 0x02
#define BUF_MASK                    BUF_BASE_ADDR + 0x03
#define BUF_INIT                    BUF_BASE_ADDR + 0x04
#define BUF_FREE_BUF_CACHE_0        BUF_BASE_ADDR + 0x05
#define BUF_FREE_BUF_CACHE_1        BUF_BASE_ADDR + 0x07
#define BUF_FREE_BUF_CACHE_2        BUF_BASE_ADDR + 0x09
#define BUF_FREE_BUF_CACHE_3        BUF_BASE_ADDR + 0x0B
#define BUF_FREE_BUF_CACHE_4        BUF_BASE_ADDR + 0x0D
#define BUF_FREE_BUF_CACHE_5        BUF_BASE_ADDR + 0x0F
#define BUF_FREE_BUF_CACHE_6        BUF_BASE_ADDR + 0x11
#define BUF_FREE_BUF_CACHE_7        BUF_BASE_ADDR + 0x13
#define BUF_FREE_BUF_CACHE_8        BUF_BASE_ADDR + 0x15
#define BUF_FREE_BUF_CACHE_9        BUF_BASE_ADDR + 0x17
#define BUF_FREE_LIST_PTR           BUF_BASE_ADDR + 0x19


// Forwarding Table General Configuration
#define FWD_BASE_ADDR               0x0300

#define FWD_TBL_SIZE                FWD_BASE_ADDR + 0x00
#define FWD_BASE_ADDR_CFG           FWD_BASE_ADDR + 0x01
#define FWD_HASH_ALG                FWD_BASE_ADDR + 0x02