📄 piportmp.c
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/*
* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
* All rights reserved.
*
* This software is copyrighted by and is the sole property of
* VIA Networking Technologies, Inc. This software may only be used
* in accordance with the corresponding license agreement. Any unauthorized
* use, duplication, transmission, distribution, or disclosure of this
* software is expressly forbidden.
*
* This software is provided by VIA Networking Technologies, Inc. "as is"
* and any express or implied warranties, including, but not limited to, the
* implied warranties of merchantability and fitness for a particular purpose
* are disclaimed. In no event shall VIA Networking Technologies, Inc.
* be liable for any direct, indirect, incidental, special, exemplary, or
* consequential damages.
*
*
* File: piportmp.c
*
* Purpose: Logical and physical port mapping functions
*
* Author: Tevin Chen
*
* Date: Jan 08, 2002
*
* Functions:
*
* Revision History:
*
*/
#include "swreg.h"
#include "swtrk.h"
#include "piportmp.h"
#include "pidef.h"
/*--------------------- Static Definitions -------------------------*/
#ifdef PORT_MAP_PANEL_DEFAULT
// Desired Port Panel modified by heavychen for 16 ports
// 01 03 05 07 09 11 13 15 (17 19 21 23)
// 00 02 04 06 08 10 12 14 (16 18 20 22)
// Physical Port Panel
// 09 11 13 15 17 19 21 23 (01 03 05 07)
// 08 10 12 14 16 18 20 22 (00 02 04 06)
static DIRECT_MEMTYPE_CODE UINT8 s_abyPanelToPhyPortMap[SWITCH_PORT_NUM] =
{
0, 1, 2, 3, 4, 5, 6, 7,
//phy port 0~7 no use in fact
#ifndef __ASIC_VT6524
24, 25
#endif
};
static DIRECT_MEMTYPE_CODE UINT8 s_abyPhyToPanelPortMap[SWITCH_PORT_NUM] =
{
0, 1, 2, 3, 4, 5, 6, 7,
#ifndef __ASIC_VT6524
24, 25
#endif
};
#endif
/*--------------------- Static Classes ----------------------------*/
/*--------------------- Static Variables --------------------------*/
/*--------------------- Static Macros -----------------------------*/
/*--------------------- Export Variables --------------------------*/
//
// Definition used for UI
//
// Definition of port names
DIRECT_MEMTYPE_CODE PSTR g_aszPortNameTable[SWITCH_PORT_NUM+SWITCH_TRUNK_GRP_NUM] =
{
"PORT1 ", "PORT2 ", "PORT3 ", "PORT4 ", "PORT5 ", "PORT6 ", "PORT7 ", "PORT8 ",
#ifndef __ASIC_VT6524
"MOD1 ", "MOD2 ",
#endif
"TRUNK1", "TRUNK2", "TRUNK3", "TRUNK4", "TRUNK5", "TRUNK6", "TRUNK7"
};
// Define port id to name mapping
DIRECT_MEMTYPE_CODE UINT8 g_abyPanelIdToNameMap[SWITCH_PORT_NUM+SWITCH_TRUNK_GRP_NUM] =
{
0, 1, 2, 3, 4, 5, 6, 7,
24, 25, 26, 27, 28, 29, 30,
#ifndef __ASIC_VT6524
31, 32
#endif
};
// Logical id list
UINT8 g_byLogIdNum;
UINT8 g_bySingleMegaLogIdNum; // for sniff config
#ifndef __ASIC_VT6524
UINT8 g_byMegaLogIdNum; // for rate ctrl config
#endif
UINT8 g_abyLogIdList[SWITCH_PORT_NUM];
/*--------------------- Static Functions --------------------------*/
/*--------------------- Internal Definitions ----------------------*/
// Definition to make statements more readable
#define pSPortTrkCfg(byCfg) ((SPortTrkCfg*)&byCfg)
/*--------------------- Export Functions --------------------------*/
//
// Transfer between logical id/ptr and physical id
//
UINT8 PIPORTMP_byLogIdToPhyId (UINT8 byLogId) DIRECT_FUNTYPE_REENT
{
// If logical id out of single port range, return ENTRY_END_FLAG
if (byLogId >= SWITCH_PORT_NUM)
return ENTRY_END_FLAG;
// If single port, return physical id
return s_abyPanelToPhyPortMap[byLogId];
}
UINT8 PORTMPbyPhyIdToLog (UINT8 byPhyId, BOOL bIfLogPtr) DIRECT_FUNTYPE_REENT
{
UINT8 byCfg, si;
// If phy id invalid, return ENTRY_END_FLAG
if (byPhyId >= SWITCH_PORT_NUM)
return ENTRY_END_FLAG;
// Check trunk config of current port
SWREG_vReadB((UINT16)(FWD_TRUNK_CFG_BASE + byPhyId), &byCfg);
// If phy id maps to a single port, return log id/pointer of port
if (byCfg == 0) {
for (si = 0; si < g_byLogIdNum; si++) {
if ( s_abyPhyToPanelPortMap[byPhyId] == g_abyLogIdList[si] ) {
if (bIfLogPtr)
return si;
else
return g_abyLogIdList[si];
}
}
}
// If phy id maps to a trunk group, return log id/pointer of group
else {
for (si = g_byLogIdNum; si > 0; si--) {
if ( pSPortTrkCfg(byCfg)->f3GrpId == (g_abyLogIdList[si-1]- PORTMAP_BASE_TRKGRP_LOG_ID + 1) ) {
if (bIfLogPtr)
return si-1;
else
return g_abyLogIdList[si-1];
}
}
}
return ENTRY_END_FLAG;
}
//
// Transfer from logical id to physical mask
//
UINT32 PIPORTMP_dwLogIdToPhyMsk (UINT8 byLogId) DIRECT_FUNTYPE_REENT
{
UINT8 byCfg, si = SWITCH_TRUNKABLE_PORT_NUM-1;
UINT32 dwPhyMsk;
// Handle trunk group
if (byLogId >= PORTMAP_BASE_TRKGRP_LOG_ID) {
// Find all members of trunk group in hardware and transfer into physical id mask
dwPhyMsk = 0;
while (1) {
// OR member into physical mask
SWREG_vReadB((UINT16)(FWD_TRUNK_CFG_BASE + si), &byCfg);
if ( pSPortTrkCfg(byCfg)->f3GrpId == (byLogId - PORTMAP_BASE_TRKGRP_LOG_ID + 1) )
dwPhyMsk |= 0x01;
// Decide whether or not the loop ends
if (si > 0) {
dwPhyMsk <<= 1;
si--;
}
else
break;
}
}
// Handle single port
else {
dwPhyMsk = 0x01;
dwPhyMsk <<= s_abyPanelToPhyPortMap[byLogId];
}
return dwPhyMsk;
}
//
// Transfer between logical id/ptr mask and physical mask
//
UINT32 PORTMPdwLogMskToPhyMsk (UINT32 dwLogMsk, BOOL bIfLogPtrMsk) DIRECT_FUNTYPE_REENT
{
UINT32 dwPhyMsk = 0;
UINT8 si;
for (si = 0; si < SWITCH_PORT_NUM + SWITCH_TRUNK_GRP_NUM; si++) {
if ( dwLogMsk & 0x01 ) {
if (bIfLogPtrMsk)
dwPhyMsk |= PIPORTMP_dwLogPtrToPhyMsk(si);
else
dwPhyMsk |= PIPORTMP_dwLogIdToPhyMsk(si);
}
dwLogMsk >>= 1;
}
return dwPhyMsk;
}
#define SHIFT_BUF_32_BIT 0x00000001UL // Used only in this function
UINT32 PORTMPdwPhyMskToLogMsk (UINT32 dwPhyMsk, BOOL bIfLogPtrMsk) DIRECT_FUNTYPE_REENT
{
UINT32 dwLogMsk = 0;
UINT8 si;
for (si = 0; si < SWITCH_PORT_NUM; si++) {
if ( dwPhyMsk & 0x01 ) {
if (bIfLogPtrMsk)
dwLogMsk |= ( SHIFT_BUF_32_BIT << PIPORTMP_byPhyIdToLogPtr(si) );
else
dwLogMsk |= ( SHIFT_BUF_32_BIT << PIPORTMP_byPhyIdToLogId(si) );
}
dwPhyMsk >>= 1;
}
return dwLogMsk;
}
//
// Update logical id list
//
void PIPORTMP_vUpdateLogIdList (void) DIRECT_FUNTYPE_REENT
{
UINT8 byValidGrpMsk = 0, byLogPtr = 0, byTmp, si;
// Add single ports into mapping array
for (si = 0; si < UI_SWITCH_TRUNKABLE_PORT_NUM; si++) {
SWREG_vReadB((UINT16)(FWD_TRUNK_CFG_BASE + s_abyPanelToPhyPortMap[si]), &byTmp);
if (byTmp == 0) { // If single port, put panel id directly
g_abyLogIdList[byLogPtr] = si;
byLogPtr++;
}
else // If trunk group, log it
byValidGrpMsk |= ( 0x01 << (pSPortTrkCfg(byTmp)->f3GrpId - MIN_TRK_GRP_ID) );
}
// Log single mega port number
g_bySingleMegaLogIdNum = byLogPtr;
// Add trunk groups into mapping array
byTmp = 0x01;
for (si = 0; si < SWITCH_TRUNK_GRP_NUM; si++) {
if ( byValidGrpMsk & byTmp ) {
g_abyLogIdList[byLogPtr] = PORTMAP_BASE_TRKGRP_LOG_ID + si;
byLogPtr++;
}
byTmp <<= 1;
}
#ifndef __ASIC_VT6524
g_byMegaLogIdNum = byLogPtr;
for (si = 0; si < SWITCH_GIGA_PORT_NUM; si++) {
if ( PIMOD_byGetModuleType(si) != MOD_CARD_NA ) {
g_abyLogIdList[byLogPtr] = SWITCH_GIGA_PORT_ID_BASE + si;
byLogPtr++;
}
}
#endif
// Add end of group into mapping array
g_byLogIdNum = byLogPtr;
for (; byLogPtr < SWITCH_PORT_NUM; byLogPtr++)
g_abyLogIdList[byLogPtr] = ENTRY_END_FLAG;
}
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