pisystem.c

VIA VT6524 8口网管交换机源码

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    pisystem.c
 *
 * Purpose: System initialization/booting operations
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 * Functions:
 *
 * Revision History:
 *
 */


#if !defined(__PLATFORM_H__)
#include "platform.h"
#endif
#include "ttyio.h"
#include "swmii.h"
#include "swsys.h"
#include "pidiag.h"
#include "pieeprom.h"
#include "pigencfg.h"

#include "pipc_qos.h"

#ifdef __MODULE_WEB_SMART
    #include "taskweb.h"
    #include "piipcfg.h"
    #include "swpkt.h"
    #include "sweep.h"
#endif


static DIRECT_MEMTYPE_CODE PSTR s_strFailPass[] = {"FAIL", "PASS"};




BOOL s_bSwitchDiag(void) DIRECT_FUNTYPE_REENT
{
    BOOL   bResult;

    TTYvClearScrn();
    TTYvPutString("\nSystem Diagnosing:\n");

    TTYvPutString("\nSwitch Register R/W Test .. ");
    bResult = PIDIAG_bRegReadWriteTest();
    TTYvPutString(s_strFailPass[bResult]);
    if (! bResult)
        return FALSE;

    TTYvPutString("\nPhy Register R/W Test ..... ");
    if ( !PIDIAG_bMiiReadWriteTest(0) )
        bResult = FALSE;
    else
        bResult = TRUE;
    TTYvPutString(s_strFailPass[bResult]);
    if (! bResult)
        return FALSE;

    TTYvPutString("\nSRAM Biult_In_Self_Test ... ");
    bResult = PIDIAG_bSramBIST();
    TTYvPutString(s_strFailPass[bResult]);
    if (! bResult)
        return FALSE;

    TTYvPutString("\nEEPROM R/W Test ........... ");
    bResult = PIDIAG_bEepromReadWriteTest();
    TTYvPutString(s_strFailPass[bResult]);
    if (! bResult)
        return FALSE;

    return TRUE;
}


#ifdef __MODULE_WEB_SMART

void PISYS_vSetHwFromEep(UConfigBuf* pUCfgBuf) DIRECT_FUNTYPE_REENT
{
/*#ifndef __ASIC_VT6524
    // init module cards
    PIMOD_vDetectModuleCard();
#endif*/

    // Setting trunk will update LogId list for port mapping
    PITRK_vSetHwFromEep((STrkPageCfg*)pUCfgBuf);

    PIPORT_vSetHwFromEep((SPortPageCfg*)pUCfgBuf);

/*#ifndef __ASIC_VT6524
    PIQOS_vSetHwFromEep((SQosPageCfg*)pUCfgBuf);
#endif

#ifdef __ASIC_VT6526
    PIRATE_vSetHwFromEep((SRatePageCfg*)pUCfgBuf);
#endif*/

    PIVLAN_vSetHwFromEep((SVlanPageCfg*)pUCfgBuf);
    PIVLNFLT_vSetHwFromEep((SVlanIngrFilterPageCfg*)pUCfgBuf);

    PIMISC_vSetHwFromEep((SMiscPageCfg*)pUCfgBuf);

    PISNF_vSetHwFromEep((SSniffPageCfg*)pUCfgBuf);

    PIIPCONF_vSetHwFromEep((SIpConfPageCfg*)pUCfgBuf);
}

void PISYS_vSwitchWriteDefault(UConfigBuf* pUCfgBuf) DIRECT_FUNTYPE_REENT
{
    PIEEP_vSetVerAndSig();

    PIPORT_vSetEepDefault((SPortPageCfg*)pUCfgBuf);

#ifndef __ASIC_VT6524
    PIQOS_vSetEepDefault((SQosPageCfg*)pUCfgBuf);
#endif
#ifdef __ASIC_VT6526
    PIRATE_vSetEepDefault((SRatePageCfg*)pUCfgBuf);
#endif

    PITRK_vSetEepDefault((STrkPageCfg*)pUCfgBuf);

    PIVLAN_vSetEepDefault((SVlanPageCfg*)pUCfgBuf);
    PIVLNFLT_vSetEepDefault((SVlanIngrFilterPageCfg*)pUCfgBuf);

    PIMISC_vSetEepDefault((SMiscPageCfg*)pUCfgBuf);

    PISNF_vSetEepDefault((SSniffPageCfg*)pUCfgBuf);

    PIADM_vSetEepDefault();

    PIIPCONF_vSetEepDefault((SIpConfPageCfg*)pUCfgBuf);
}

#endif

void PISYS_vSwitchBoot(void) DIRECT_FUNTYPE_REENT
{
#ifdef __MODULE_WEB_SMART
    BYTE si;
#endif

    // CPU init misc setting
//    PLATvCpuInit();
    PLATvTimer0Init();
    PLATvTimer0Stop();
    PIMISC_vStopAutoLogout();

    // Set CPU IRQ initial mask
    PLATvCpuIrqMskInit();

    // Trigger MAC & PHY reset signal
    SWSYS_vResetSystem();

    // Diagnose system
    while(!s_bSwitchDiag()) {
        TTYvPutString("\n\nThere may be some problems in your hardware.");
        TTYvPutString("\nPlease contact your manufacturer.");
        TTYcGetChar();
    }

    // Set system initial hardware configuration
    SWSYS_vSwitchInit();

    // check eeprom checksum, version and signature
    TTYvPutString("\nEEPROM Content Check ...... ");
   // if (!( PIEEP_bCheckVerAndSig() && PIEEP_bVerifyChecksum() ))
   if (!( PIEEP_bCheckVerAndSig() ))
    {
        TTYvPutString(s_strFailPass[0]);

        TTYvPutString("\n\nWriting default setting into EEPROM .. ");
#ifdef __MODULE_WEB_SMART
        PISYS_vSwitchWriteDefault(&g_UCfgBuf);
#else
        PISYS_vSwitchWriteDefault();
#endif
        TTYvPutString("OK");
    }
    else
        TTYvPutString(s_strFailPass[1]);

    // Load eeprom config and set to hardware
    TTYvPutString("\n\nInitializing user configuration ... ");
#ifdef __MODULE_WEB_SMART
    PISYS_vSetHwFromEep(&g_UCfgBuf);
#else
    PISYS_vSetHwFromEep();
#endif
    TTYvPutString("OK");

    // Enable phy autopolling
    SWMII_vSetAutoPollOn();

#ifdef __ASIC_VT6526
    // Set giga 1 config from strapping
    if (SWPORT_bIfTbiPort(SWITCH_GIGA_PORT_ID_BASE))
        SWREG_vBitsOn(PHY_GMII_MII_AUTOPOLL_CFG, PTN_PHY_GIGA1_TBI);

    // Set giga 2 config from strapping
    if (SWPORT_bIfTbiPort(SWITCH_GIGA_PORT_ID_BASE+1))
        SWREG_vBitsOn(PHY_GMII_MII_AUTOPOLL_CFG, PTN_PHY_GIGA2_TBI);
#endif

#ifdef __MODULE_WEB_SMART
    // It should be run when MAC resets and after hardware are all ready.
    // get mac address from eeprom and set it to NTZg_abyMyEthAddr
    for (si=0; si<6; si++)
    {
        SWEEP_bReadB(EEP_ADDR_MAC_ADDR+si, NTZg_abyMyEthAddr+si);
        SWREG_vWriteB(CPU_SWITCH_MAC+si, NTZg_abyMyEthAddr[si]);
    }
#endif

    PLATvTimer0Start();
}

void PISYS_vSwitchReBoot(void) DIRECT_FUNTYPE_REENT
{
#ifdef __ASIC_VT6526D
    if (CHIP_VT3221 == SWSYS_byGetChipType() && SWREG_bIfBitsOff(GLOBAL_CHIP_CFG, 0x04))
    {   // if 3221 mode init
        SWSYS_vSwitchColdBoot();    // will reset CPU
        while (1)
            ;   // wait for MAC reset CPU
    }
#endif
      TTYvPutString("Jump to PC=0");
	PLATvCpuReset();
}