📄 main.s
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ldi R24,1
sts _clock_speed,R24
.dbline 235
; if ((msg_buffer[2]) >= 1 ) clock_speed=SPI_SPEED_2MHZ;
lds R24,_msg_buffer+2
cpi R24,1
brlo L53
X24:
.dbline 235
ldi R24,1
sts _clock_speed,R24
L53:
.dbline 236
; if ((msg_buffer[2]) >= 2 ) clock_speed=SPI_SPEED_1MHZ;
lds R24,_msg_buffer+2
cpi R24,2
brlo L56
X25:
.dbline 236
ldi R24,2
sts _clock_speed,R24
L56:
.dbline 237
; if ((msg_buffer[2]) >= 4 ) clock_speed=SPI_SPEED_500KHZ;
lds R24,_msg_buffer+2
cpi R24,4
brlo L59
X26:
.dbline 237
ldi R24,3
sts _clock_speed,R24
L59:
.dbline 238
; if ((msg_buffer[2]) >= 8 ) clock_speed=SPI_SPEED_250KHZ;
lds R24,_msg_buffer+2
cpi R24,8
brlo L62
X27:
.dbline 238
ldi R24,4
sts _clock_speed,R24
L62:
.dbline 239
; if ((msg_buffer[2]) >= 16 ) clock_speed=SPI_SPEED_125KHZ;
lds R24,_msg_buffer+2
cpi R24,16
brlo L65
X28:
.dbline 239
ldi R24,5
sts _clock_speed,R24
L65:
.dbline 240
; if ((msg_buffer[2]) >= 32 ) clock_speed=SPI_SPEED_62KHZ;
lds R24,_msg_buffer+2
cpi R24,32
brlo L68
X29:
.dbline 240
ldi R24,6
sts _clock_speed,R24
L68:
.dbline 241
; if (EEPROMread((int)&eeprom_sck_period)!=clock_speed) EEPROMwrite((int)&eeprom_sck_period,clock_speed);
ldi R16,<_eeprom_sck_period
ldi R17,>_eeprom_sck_period
xcall _EEPROMread
lds R2,_clock_speed
cp R16,R2
breq L71
X30:
.dbline 241
mov R18,R2
ldi R16,<_eeprom_sck_period
ldi R17,>_eeprom_sck_period
xcall _EEPROMwrite
L71:
.dbline 242
; spi_set_speed(clock_speed);
lds R16,_clock_speed
xcall _spi_set_speed
.dbline 243
; break;
xjmp L49
L73:
.dbline 245
; case PARAM_RESET_POLARITY:
; reset_polarity = msg_buffer[2];
lds R2,_msg_buffer+2
sts _reset_polarity,R2
.dbline 246
; break;
xjmp L49
L75:
.dbline 248
; case PARAM_CONTROLLER_INIT:
; param_controller_init = msg_buffer[2];
lds R2,_msg_buffer+2
sts _param_controller_init,R2
.dbline 249
; break;
L48:
L49:
.dbline 252
; }
;
; num_bytes = 2;
ldi R24,2
ldi R25,0
movw R10,R24
.dbline 253
; msg_buffer[0] = CMD_SET_PARAMETER;
sts _msg_buffer,R24
.dbline 254
; msg_buffer[1] = STATUS_CMD_OK;
clr R2
sts _msg_buffer+1,R2
.dbline 255
; }
xjmp L47
L46:
.dbline 259
; //////////////////////////////////////
; //CMD_GET_PARAMETER
; //////////////////////////////////////
; else if (cmd==CMD_GET_PARAMETER)
ldd R24,y+10
cpi R24,3
breq X139
xjmp L79
X139:
X31:
.dbline 260
; {
.dbline 261
; switch (msg_buffer[1])
lds R12,_msg_buffer+1
mov R24,R12
cpi R24,144
breq L87
X32:
cpi R24,145
breq L88
X33:
cpi R24,146
breq L89
X34:
ldi R24,146
cp R24,R12
brlo L94
X35:
L93:
mov R24,R12
cpi R24,128
breq L85
X36:
cpi R24,129
breq L86
X37:
xjmp L81
L94:
mov R24,R12
cpi R24,152
breq L90
X38:
cpi R24,152
brlo L81
X39:
L95:
mov R24,R12
cpi R24,158
breq L91
X40:
cpi R24,159
breq L92
X41:
xjmp L81
L85:
.dbline 264
; {
; case PARAM_BUILD_NUMBER_LOW:
; tmp = CONFIG_PARAM_BUILD_NUMBER_LOW;
clr R0
std y+18,R0
.dbline 265
; break;
xjmp L82
L86:
.dbline 267
; case PARAM_BUILD_NUMBER_HIGH:
; tmp = CONFIG_PARAM_BUILD_NUMBER_HIGH;
clr R0
std y+18,R0
.dbline 268
; break;
xjmp L82
L87:
.dbline 270
; case PARAM_HW_VER:
; tmp = CONFIG_PARAM_HW_VER;
ldi R24,15
std y+18,R24
.dbline 271
; break;
xjmp L82
L88:
.dbline 273
; case PARAM_SW_MAJOR:
; tmp = CONFIG_PARAM_SW_MAJOR;
ldi R24,2
std y+18,R24
.dbline 274
; break;
xjmp L82
L89:
.dbline 276
; case PARAM_SW_MINOR:
; tmp = CONFIG_PARAM_SW_MINOR;
ldi R24,10
std y+18,R24
.dbline 277
; break;
xjmp L82
L90:
.dbline 279
; case PARAM_SCK_DURATION:
; tmp = clock_speed;
lds R2,_clock_speed
std y+18,R2
.dbline 280
; break;
xjmp L82
L91:
.dbline 282
; case PARAM_RESET_POLARITY:
; tmp = reset_polarity;
lds R2,_reset_polarity
std y+18,R2
.dbline 283
; break;
xjmp L82
L92:
.dbline 285
; case PARAM_CONTROLLER_INIT:
; tmp = param_controller_init;
lds R2,_param_controller_init
std y+18,R2
.dbline 286
; break;
L81:
L82:
.dbline 289
; }
;
; num_bytes = 3;
ldi R24,3
ldi R25,0
movw R10,R24
.dbline 290
; msg_buffer[0] = CMD_GET_PARAMETER;
sts _msg_buffer,R24
.dbline 291
; msg_buffer[1] = STATUS_CMD_OK;
clr R2
sts _msg_buffer+1,R2
.dbline 292
; msg_buffer[2] = tmp;
ldd R0,y+18
sts _msg_buffer+2,R0
.dbline 293
; }
xjmp L80
L79:
.dbline 297
; //////////////////////////////////////
; //CMD_LOAD_ADDRESS
; //////////////////////////////////////
; else if (cmd==CMD_LOAD_ADDRESS)
ldd R24,y+10
cpi R24,6
breq X140
xjmp L98
X140:
X42:
.dbline 298
; {
.dbline 299
; address = ((unsigned long)msg_buffer[1])<<24;
ldi R24,24
ldi R25,0
lds R16,_msg_buffer+1
clr R17
clr R18
clr R19
st -y,R24
xcall lsl32
sts _address+1,R17
sts _address,R16
sts _address+2+1,R19
sts _address+2,R18
.dbline 300
; address |= ((unsigned long)msg_buffer[2])<<16;
lds R2,_msg_buffer+2
clr R3
clr R4
clr R5
movw R4,R2
clr R2
clr R3
movw R6,R16
movw R8,R18
or R6,R2
or R7,R3
or R8,R4
or R9,R5
sts _address+1,R7
sts _address,R6
sts _address+2+1,R9
sts _address+2,R8
.dbline 301
; address |= ((unsigned long)msg_buffer[3])<<8;
ldi R24,8
ldi R25,0
lds R16,_msg_buffer+3
clr R17
clr R18
clr R19
st -y,R24
xcall lsl32
lds R4,_address+2
lds R5,_address+2+1
lds R2,_address
lds R3,_address+1
or R2,R16
or R3,R17
or R4,R18
or R5,R19
sts _address+1,R3
sts _address,R2
sts _address+2+1,R5
sts _address+2,R4
.dbline 302
; address |= ((unsigned long)msg_buffer[4]);
lds R2,_msg_buffer+4
clr R3
clr R4
clr R5
lds R8,_address+2
lds R9,_address+2+1
lds R6,_address
lds R7,_address+1
or R6,R2
or R7,R3
or R8,R4
or R9,R5
sts _address+1,R7
sts _address,R6
sts _address+2+1,R9
sts _address+2,R8
.dbline 304
;
; num_bytes = 2;
ldi R24,2
ldi R25,0
movw R10,R24
.dbline 305
; msg_buffer[0] = CMD_LOAD_ADDRESS;
ldi R24,6
sts _msg_buffer,R24
.dbline 306
; msg_buffer[1] = STATUS_CMD_OK;
clr R2
sts _msg_buffer+1,R2
.dbline 307
; }
xjmp L99
L98:
.dbline 311
; //////////////////////////////////////
; //CMD_ENTER_PROGMODE_ISP
; //////////////////////////////////////
; else if (cmd==CMD_ENTER_PROGMODE_ISP)
ldd R24,y+10
cpi R24,16
breq X141
xjmp L105
X141:
X43:
.dbline 312
; {
.dbline 325
; //msg_buffer[1] //timeout //Command time-out (in ms)
; //msg_buffer[2] //stabDelay //Delay (in ms) used for pin stabilization
; //msg_buffer[3] //cmdexeDelay //Delay (in ms) in connection with the EnterProgMode command execution
; //msg_buffer[4] //synchLoops //Number of synchronization loops
; //msg_buffer[5] //byteDelay //Delay (in ms) between each byte in the EnterProgMode command.
; //msg_buffer[6] //pollValue //Poll value: 0x53 for AVR, 0x69 for AT89xx
; //msg_buffer[7] //pollIndex //Start address, received byte: 0 = no polling, 3 = AVR, 4 = AT89xx
; //msg_buffer[8] //cmd1 //Command Byte # 1 to be transmitted
; //msg_buffer[9] //cmd2 //Command Byte # 2 to be transmitted
; //msg_buffer[10]//cmd3 //Command Byte # 3 to be transmitted
; //msg_buffer[11]//cmd4 //Command Byte # 4 to be transmitted
;
; prgmode=1;
ldi R24,1
sts _prgmode,R24
.dbline 327
;
; spi_enable();
xcall _spi_enable
.dbline 329
;
; wait_ms(msg_buffer[2]);
lds R16,_msg_buffer+2
clr R17
xcall _wait_ms
.dbline 331
;
; LED_GN_ON;
sbi 0x12,2
.dbline 332
; LED_RT_ON;
sbi 0x12,3
.dbline 335
;
; //Try to get connection with the target chip
; for (i=0;i<msg_buffer[4];i++)
clr R12
clr R13
xjmp L111
L108:
.dbline 336
; {
.dbline 338
; //spi_transfer_16(0xAC53);
; spi_transfer_8(msg_buffer[8]);
lds R16,_msg_buffer+8
xcall _spi_transfer_8
.dbline 339
; wait_ms(msg_buffer[5]);
lds R16,_msg_buffer+5
clr R17
xcall _wait_ms
.dbline 340
; spi_transfer_8(msg_buffer[9]);
lds R16,_msg_buffer+9
xcall _spi_transfer_8
.dbline 341
; wait_ms(msg_buffer[5]);
lds R16,_msg_buffer+5
clr R17
xcall _wait_ms
.dbline 343
;
; if (msg_buffer[7]==3)
lds R24,_msg_buffer+7
cpi R24,3
brne L117
X44:
.dbline 344
; {
.dbline 345
; tmp=spi_transfer_8(msg_buffer[10]);
lds R16,_msg_buffer+10
xcall _spi_transfer_8
mov R14,R16
.dbline 346
; wait_ms(msg_buffer[5]);
lds R16,_msg_buffer+5
clr R17
xcall _wait_ms
.dbline 347
; spi_transfer_8(msg_buffer[11]);
lds R16,_msg_buffer+11
xcall _spi_transfer_8
.dbline 348
; wait_ms(msg_buffer[5]);
lds R16,_msg_buffer+5
clr R17
xcall _wait_ms
.dbline 349
; }
xjmp L118
L117:
.dbline 351
; else
; {
.dbline 352
; spi_transfer_8(msg_buffer[10]);
lds R16,_msg_buffer+10
xcall _spi_transfer_8
.dbline 353
; wait_ms(msg_buffer[5]);
lds R16,_msg_buffer+5
clr R17
xcall _wait_ms
.dbline 354
; tmp=spi_transfer_8(msg_buffer[11]);
lds R16,_msg_buffer+11
xcall _spi_transfer_8
std y+15,R17
std y+14,R16
movw R14,R16
.dbline 355
; wait_ms(msg_buffer[5]);
lds R16,_msg_buffer+5
clr R17
xcall _wait_ms
.dbline 356
; }
L118:
.dbline 358
;
; if ((tmp==msg_buffer[6])||(msg_buffer[7]==0))
lds R2,_msg_buffer+6
cp R14,R2
breq L132
X45:
lds R2,_msg_buffer+7
tst R2
brne L128
X46:
L132:
.dbline 359
; {
.dbline 360
; LED_GN_OFF;
ldi R24,-5
ldi R25,-1
in R2,0x12
and R2,R24
out 0x12,R2
.dbline 361
; LED_RT_ON;
sbi 0x12,3
.dbline 362
; i=0xFF;
ldi R24,255
ldi R25,0
movw R12,R24
.dbline 363
; break;
xjmp L110
L128:
.dbline 366
; }
;
; spi_clock_pulse();
xcall _spi_clock_pulse
.dbline 367
; }
L109:
.dbline 335
movw R24,R12
adiw R24,1
movw R12,R24
L111:
.dbline 335
lds R2,_msg_buffer+4
clr R3
cp R12,R2
cpc R13,R3
brsh X142
xjmp L108
X142:
X47:
L110:
.dbline 369
;
; num_bytes = 2;
ldi R24,2
ldi R25,0
movw R10,R24
.dbline 370
; msg_buffer[0] = CMD_ENTER_PROGMODE_ISP;
ldi R24,16
sts _msg_buffer,R24
.dbline 372
;
; if (i==0xFF)
movw R24,R12
cpi R24,255
ldi R30,0
cpc R25,R30
brne L133
X48:
.dbline 373
; {
.dbline 374
; msg_buffer[1] = STATUS_CMD_OK;
clr R2
sts _msg_buffer+1,R2
.dbline 375
; }
xjmp L106
L133:
.dbline 377
; else
; {
.dbline 378
; msg_buffer[1] = STATUS_CMD_FAILED;
ldi R24,192
sts _msg_buffer+1,R24
.dbline 379
; }
.dbline 380
; }
xjmp L106
L105:
.dbline 384
; //////////////////////////////////////
; //CMD_LEAVE_PROGMODE_ISP
; //////////////////////////////////////
; else if (cmd==CMD_LEAVE_PROGMODE_ISP)
ldd R24,y+10
cpi R24,17
brne L137
X49:
.dbline 385
; {
.dbline 386
; prgmode=0;
clr R2
sts _prgmode,R2
.dbline 388
;
; spi_disable();
xcall _spi_disable
.dbline 390
;
; LED_RT_OFF;
ldi R24,-9
ldi R25,-1
in R2,0x12
and R2,R24
out 0x12,R2
.dbline 391
; LED_GN_ON;
sbi 0x12,2
.dbline 393
;
; num_bytes = 2;
ldi R24,2
ldi R25,0
movw R10,R24
.dbline 394
; msg_buffer[0] = CMD_LEAVE_PROGMODE_ISP;
ldi R24,17
sts _msg_buffer,R24
.dbline 395
; msg_buffer[1] = STATUS_CMD_OK;
clr R2
sts _msg_buffer+1,R2
.dbline 396
; }
xjmp L138
L137:
.dbline 400
; //////////////////////////////////////
; //CMD_CHIP_ERASE_ISP
; //////////////////////////////////////
; else if (cmd==CMD_CHIP_ERASE_ISP)
ldd R24,y+10
cpi R24,18
brne L140
X50:
.dbline 401
; {
.dbline 402
; spi_transfer_8(msg_buffer[3]);
lds R16,_msg_buffer+3
xcall _spi_transfer_8
.dbline 403
; spi_transfer_8(msg_buffer[4]);
lds R16,_msg_buffer+4
xcall _spi_transfer_8
.dbline 404
; spi_transfer_8(msg_buffer[5]);
lds R16,_msg_buffer+5
xcall _spi_transfer_8
.dbline 405
; spi_transfer_8(msg_buffer[6]);
lds R16,_msg_buffer+6
xcall _spi_transfer_8
.dbline 409
;
; //Newer AVR's seems to have a busy bit
; //cant test this because I don't have any of these new chips
; if (msg_buffer[2]==0)
lds R2,_msg_buffer+2
tst R2
brne L151
X51:
.dbline 410
; {
.dbline 411
; wait_ms(msg_buffer[1]);
lds R16,_msg_buffer+1
clr R17
xcall _wait_ms
.dbline 412
; }
xjmp L147
L150:
.dbline 415
; else //if(msg_buffer[2]==1)
; {
; while (spi_transfer_32(0xF0000000)&1);
L151:
.dbline 415
ldi R16,0
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