📄 spi.lis
字号:
.module spi.c
.area text(rom, con, rel)
0000 .dbfile E:\单片机\源程序\Snail_mkII\STK500_V2\ICC\spi.c
.area data(ram, con, rel)
0000 .dbfile E:\单片机\源程序\Snail_mkII\STK500_V2\ICC\spi.c
0000 _use_sw_spi:
0000 .blkb 1
.area idata
0000 00 .byte 0
.area data(ram, con, rel)
0001 .dbfile E:\单片机\源程序\Snail_mkII\STK500_V2\ICC\spi.c
.area text(rom, con, rel)
0000 .dbfile E:\单片机\源程序\Snail_mkII\STK500_V2\ICC\spi.c
0000 .dbfunc e spi_enable _spi_enable fV
0000 ; i0 -> R20
.even
0000 _spi_enable::
0000 4A93 st -y,R20
0002 .dbline -1
0002 .dbline 48
0002 ; /** \file
0002 ; <b>SPI</b><br>
0002 ; Autor: Matthias Wei遝r<br>
0002 ; Copyright 2005: Matthias Wei遝r<br>
0002 ; License: QPL (see license.txt)
0002 ; <hr>
0002 ; */
0002 ; #include <iccioavr.h>
0002 ; #include <eeprom.h>
0002 ; #include <macros.h>
0002 ; #include "spi.h"
0002 ; #include "tools.h"
0002 ; #include "extern_vars.h"
0002 ;
0002 ; static unsigned char use_sw_spi = 0;
0002 ;
0002 ;
0002 ; #if defined(ATMega8)
0002 ; // HW Normal M8 version
0002 ; #define MOSI_SET PORTB|=BIT(3);
0002 ; #define MOSI_CLEAR PORTB&=~BIT(3);
0002 ;
0002 ; #define MISO_IN (PINB & BIT(4))
0002 ; #define SCK_SET PORTB |= BIT(5);
0002 ; #define SCK_CLEAR PORTB &= ~BIT(5);
0002 ;
0002 ; #define DDR_MOSI_OUT DDRB |= BIT(3);
0002 ; #define DDR_MOSI_IN DDRB &= ~BIT(3);NOP();
0002 ; #define DDR_SCK_OUT DDRB |= BIT(5);
0002 ; #define DDR_SCK_IN DDRB &= ~BIT(5);NOP();
0002 ;
0002 ; #elif defined(ATMega16) || defined(ATMega32)
0002 ; // HW Snail Emluator Kit
0002 ; #define MOSI_SET PORTB |= BIT(5);
0002 ; #define MOSI_CLEAR PORTB &= ~BIT(5);
0002 ;
0002 ; #define MISO_IN (PINB & BIT(6))
0002 ; #define SCK_SET PORTB |= BIT(7);
0002 ; #define SCK_CLEAR PORTB &= ~BIT(7);
0002 ;
0002 ; #define DDR_MOSI_OUT DDRB |= BIT(5);
0002 ; #define DDR_MOSI_IN DDRB &= ~BIT(5);NOP();
0002 ; #define DDR_SCK_OUT DDRB |= BIT(7);
0002 ; #define DDR_SCK_IN DDRB &= ~BIT(7);NOP();
0002 ; #endif
0002 ;
0002 ; void spi_enable(void)
0002 ; {
0002 .dbline 51
0002 ; unsigned char i;
0002 ;
0002 ; R_RES_ON;
0002 8FEE ldi R24,-17
0004 9FEF ldi R25,-1
0006 28B2 in R2,0x18
0008 2822 and R2,R24
000A 28BA out 0x18,R2
000C .dbline 52
000C ; wait_ms(2);
000C 02E0 ldi R16,2
000E 10E0 ldi R17,0
0010 0E940000 xcall _wait_ms
0014 .dbline 56
0014 ;
0014 ; //PORTB &= BIT3_NEG & BIT5_NEG; //MOSI and SCK low
0014 ; //DDRB |= BIT3_POS | BIT5_POS; //MOSI and SCK als Ausgang
0014 ; MOSI_CLEAR;SCK_CLEAR;
0014 C598 cbi 0x18,5
0016 .dbline 56
0016 .dbline 56
0016 C798 cbi 0x18,7
0018 .dbline 56
0018 .dbline 57
0018 ; DDR_MOSI_OUT;DDR_SCK_OUT
0018 BD9A sbi 0x17,5
001A .dbline 57
001A .dbline 57
001A BF9A sbi 0x17,7
001C .dbline 59
001C ;
001C ; if (EEPROMread((int)&eeprom_sck_period) > 64)
001C 00E0 ldi R16,<_eeprom_sck_period
001E 10E0 ldi R17,>_eeprom_sck_period
0020 0E940000 xcall _EEPROMread
0024 80E4 ldi R24,64
0026 8017 cp R24,R16
0028 30F4 brsh L3
002A X0:
002A .dbline 60
002A ; {
002A .dbline 61
002A ; use_sw_spi = 1; //使用模拟SPI
002A 81E0 ldi R24,1
002C 80930000 sts _use_sw_spi,R24
0030 .dbline 62
0030 ; SPCR=0x00;
0030 2224 clr R2
0032 2DB8 out 0xd,R2
0034 .dbline 63
0034 ; }
0034 0AC0 xjmp L4
0036 L3:
0036 .dbline 65
0036 ; else
0036 ; {
0036 .dbline 66
0036 ; use_sw_spi = 0; //使用硬件SPI
0036 2224 clr R2
0038 20920000 sts _use_sw_spi,R2
003C .dbline 67
003C ; SPCR = 0x51; //SPI Master /16
003C 81E5 ldi R24,81
003E 8DB9 out 0xd,R24
0040 .dbline 68
0040 ; spi_set_speed(EEPROMread((int)&eeprom_sck_period));
0040 00E0 ldi R16,<_eeprom_sck_period
0042 10E0 ldi R17,>_eeprom_sck_period
0044 0E940000 xcall _EEPROMread
0048 25D0 xcall _spi_set_speed
004A .dbline 69
004A ; }
004A L4:
004A .dbline 71
004A ;
004A ; R_RES_OFF;
004A C49A sbi 0x18,4
004C .dbline 72
004C ; for (i=0;i<200;i++) asm("nop");
004C 4427 clr R20
004E 02C0 xjmp L8
0050 L5:
0050 .dbline 72
0050 0000 nop
0052 L6:
0052 .dbline 72
0052 4395 inc R20
0054 L8:
0054 .dbline 72
0054 483C cpi R20,200
0056 E0F3 brlo L5
0058 X1:
0058 .dbline 73
0058 ; R_RES_ON;
0058 8FEE ldi R24,-17
005A 9FEF ldi R25,-1
005C 28B2 in R2,0x18
005E 2822 and R2,R24
0060 28BA out 0x18,R2
0062 .dbline 74
0062 ; wait_ms(2);
0062 02E0 ldi R16,2
0064 10E0 ldi R17,0
0066 0E940000 xcall _wait_ms
006A .dbline -2
006A L2:
006A .dbline 0 ; func end
006A 4991 ld R20,y+
006C 0895 ret
006E .dbsym r i0 20 c
006E .dbend
006E .dbfunc e spi_disable _spi_disable fV
.even
006E _spi_disable::
006E .dbline -1
006E .dbline 79
006E ;
006E ; }
006E ;
006E ; void spi_disable(void)
006E ; {
006E .dbline 80
006E ; SPCR=0x00; //SPI aus
006E 2224 clr R2
0070 2DB8 out 0xd,R2
0072 .dbline 82
0072 ; //DDRB &= BIT3_NEG & BIT5_NEG; //MOSI und SCK als Eingang (hochohmig)
0072 ; DDR_MOSI_IN;DDR_SCK_IN;
0072 BD98 cbi 0x17,5
0074 .dbline 82
0074 0000 nop
0076 .dbline 82
0076 .dbline 82
0076 BF98 cbi 0x17,7
0078 .dbline 82
0078 0000 nop
007A .dbline 82
007A .dbline 83
007A ; R_RES_OFF;
007A C49A sbi 0x18,4
007C .dbline -2
007C L9:
007C .dbline 0 ; func end
007C 0895 ret
007E .dbend
007E .dbfunc e spi_reset _spi_reset fV
.even
007E _spi_reset::
007E .dbline -1
007E .dbline 87
007E ; }
007E ;
007E ; void spi_reset(void)
007E ; {
007E .dbline 88
007E ; R_RES_OFF;
007E C49A sbi 0x18,4
0080 .dbline 89
0080 ; wait_ms(2);
0080 02E0 ldi R16,2
0082 10E0 ldi R17,0
0084 0E940000 xcall _wait_ms
0088 .dbline 90
0088 ; R_RES_ON;
0088 8FEE ldi R24,-17
008A 9FEF ldi R25,-1
008C 28B2 in R2,0x18
008E 2822 and R2,R24
0090 28BA out 0x18,R2
0092 .dbline -2
0092 L10:
0092 .dbline 0 ; func end
0092 0895 ret
0094 .dbend
0094 .dbfunc e spi_set_speed _spi_set_speed fV
0094 ; s -> R16
.even
0094 _spi_set_speed::
0094 4A93 st -y,R20
0096 .dbline -1
0096 .dbline 107
0096 ; }
0096 ;
0096 ; /**
0096 ; Stellt die Geschwindigkeit des SPI-Busses ein (bei f=8MHz)
0096 ; 0: /2 4MHz --SPI2X
0096 ; 1 /4 2MHz
0096 ; 2: /8 1MHz --SPI2X
0096 ; 3 /16 500kHz
0096 ; 4: /32 250kHz --SPI2X
0096 ; 5 /64 125kHz
0096 ; 6: /128 62,5kHz
0096 ;
0096 ; weitere Geschwindigkeiten geplant
0096 ; -> dann per Software-SPI
0096 ; */
0096 ; void spi_set_speed(unsigned char s)
0096 ; {
0096 .dbline 109
0096 ; #if F_CPU <= 8000000
0096 ; if ((s==0)||(s==2)||(s==4)) SPSR|=1;
0096 0023 tst R16
0098 21F0 breq L15
009A X2:
009A 0230 cpi R16,2
009C 11F0 breq L15
009E X3:
009E 0430 cpi R16,4
00A0 11F4 brne L12
00A2 X4:
00A2 L15:
00A2 .dbline 109
00A2 709A sbi 0xe,0
00A4 03C0 xjmp L13
00A6 L12:
00A6 .dbline 110
00A6 ; else SPSR&=0xFE;
00A6 8EB1 in R24,0xe
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -