📄 main.lis
字号:
01C2 61C0 xjmp L46
01C4 X135:
01C4 X19:
01C4 .dbline 230
01C4 ; {
01C4 .dbline 231
01C4 ; switch (msg_buffer[1])
01C4 C0900900 lds R12,_msg_buffer+1
01C8 8C2D mov R24,R12
01CA 8839 cpi R24,152
01CC 59F0 breq L52
01CE X20:
01CE 8839 cpi R24,152
01D0 08F4 brsh X136
01D2 50C0 xjmp L48
01D4 X136:
01D4 X21:
01D4 L77:
01D4 8C2D mov R24,R12
01D6 8E39 cpi R24,158
01D8 09F4 brne X137
01DA 43C0 xjmp L73
01DC X137:
01DC X22:
01DC 8F39 cpi R24,159
01DE 09F4 brne X138
01E0 45C0 xjmp L75
01E2 X138:
01E2 X23:
01E2 48C0 xjmp L48
01E4 L52:
01E4 .dbline 234
01E4 ; {
01E4 ; case PARAM_SCK_DURATION:
01E4 ; clock_speed=SPI_SPEED_2MHZ;
01E4 81E0 ldi R24,1
01E6 80930700 sts _clock_speed,R24
01EA .dbline 235
01EA ; if ((msg_buffer[2]) >= 1 ) clock_speed=SPI_SPEED_2MHZ;
01EA 80910A00 lds R24,_msg_buffer+2
01EE 8130 cpi R24,1
01F0 18F0 brlo L53
01F2 X24:
01F2 .dbline 235
01F2 81E0 ldi R24,1
01F4 80930700 sts _clock_speed,R24
01F8 L53:
01F8 .dbline 236
01F8 ; if ((msg_buffer[2]) >= 2 ) clock_speed=SPI_SPEED_1MHZ;
01F8 80910A00 lds R24,_msg_buffer+2
01FC 8230 cpi R24,2
01FE 18F0 brlo L56
0200 X25:
0200 .dbline 236
0200 82E0 ldi R24,2
0202 80930700 sts _clock_speed,R24
0206 L56:
0206 .dbline 237
0206 ; if ((msg_buffer[2]) >= 4 ) clock_speed=SPI_SPEED_500KHZ;
0206 80910A00 lds R24,_msg_buffer+2
020A 8430 cpi R24,4
020C 18F0 brlo L59
020E X26:
020E .dbline 237
020E 83E0 ldi R24,3
0210 80930700 sts _clock_speed,R24
0214 L59:
0214 .dbline 238
0214 ; if ((msg_buffer[2]) >= 8 ) clock_speed=SPI_SPEED_250KHZ;
0214 80910A00 lds R24,_msg_buffer+2
0218 8830 cpi R24,8
021A 18F0 brlo L62
021C X27:
021C .dbline 238
021C 84E0 ldi R24,4
021E 80930700 sts _clock_speed,R24
0222 L62:
0222 .dbline 239
0222 ; if ((msg_buffer[2]) >= 16 ) clock_speed=SPI_SPEED_125KHZ;
0222 80910A00 lds R24,_msg_buffer+2
0226 8031 cpi R24,16
0228 18F0 brlo L65
022A X28:
022A .dbline 239
022A 85E0 ldi R24,5
022C 80930700 sts _clock_speed,R24
0230 L65:
0230 .dbline 240
0230 ; if ((msg_buffer[2]) >= 32 ) clock_speed=SPI_SPEED_62KHZ;
0230 80910A00 lds R24,_msg_buffer+2
0234 8032 cpi R24,32
0236 18F0 brlo L68
0238 X29:
0238 .dbline 240
0238 86E0 ldi R24,6
023A 80930700 sts _clock_speed,R24
023E L68:
023E .dbline 241
023E ; if (EEPROMread((int)&eeprom_sck_period)!=clock_speed) EEPROMwrite((int)&eeprom_sck_period,clock_speed);
023E 00E0 ldi R16,<_eeprom_sck_period
0240 10E0 ldi R17,>_eeprom_sck_period
0242 0E940000 xcall _EEPROMread
0246 20900700 lds R2,_clock_speed
024A 0215 cp R16,R2
024C 29F0 breq L71
024E X30:
024E .dbline 241
024E 222D mov R18,R2
0250 00E0 ldi R16,<_eeprom_sck_period
0252 10E0 ldi R17,>_eeprom_sck_period
0254 0E940000 xcall _EEPROMwrite
0258 L71:
0258 .dbline 242
0258 ; spi_set_speed(clock_speed);
0258 00910700 lds R16,_clock_speed
025C 0E940000 xcall _spi_set_speed
0260 .dbline 243
0260 ; break;
0260 09C0 xjmp L49
0262 L73:
0262 .dbline 245
0262 ; case PARAM_RESET_POLARITY:
0262 ; reset_polarity = msg_buffer[2];
0262 20900A00 lds R2,_msg_buffer+2
0266 20920600 sts _reset_polarity,R2
026A .dbline 246
026A ; break;
026A 04C0 xjmp L49
026C L75:
026C .dbline 248
026C ; case PARAM_CONTROLLER_INIT:
026C ; param_controller_init = msg_buffer[2];
026C 20900A00 lds R2,_msg_buffer+2
0270 20920500 sts _param_controller_init,R2
0274 .dbline 249
0274 ; break;
0274 L48:
0274 L49:
0274 .dbline 252
0274 ; }
0274 ;
0274 ; num_bytes = 2;
0274 82E0 ldi R24,2
0276 90E0 ldi R25,0
0278 5C01 movw R10,R24
027A .dbline 253
027A ; msg_buffer[0] = CMD_SET_PARAMETER;
027A 80930800 sts _msg_buffer,R24
027E .dbline 254
027E ; msg_buffer[1] = STATUS_CMD_OK;
027E 2224 clr R2
0280 20920900 sts _msg_buffer+1,R2
0284 .dbline 255
0284 ; }
0284 98C7 xjmp L47
0286 L46:
0286 .dbline 259
0286 ; //////////////////////////////////////
0286 ; //CMD_GET_PARAMETER
0286 ; //////////////////////////////////////
0286 ; else if (cmd==CMD_GET_PARAMETER)
0286 8A85 ldd R24,y+10
0288 8330 cpi R24,3
028A 09F0 breq X139
028C 43C0 xjmp L79
028E X139:
028E X31:
028E .dbline 260
028E ; {
028E .dbline 261
028E ; switch (msg_buffer[1])
028E C0900900 lds R12,_msg_buffer+1
0292 8C2D mov R24,R12
0294 8039 cpi R24,144
0296 F1F0 breq L87
0298 X32:
0298 8139 cpi R24,145
029A F9F0 breq L88
029C X33:
029C 8239 cpi R24,146
029E 01F1 breq L89
02A0 X34:
02A0 82E9 ldi R24,146
02A2 8C15 cp R24,R12
02A4 30F0 brlo L94
02A6 X35:
02A6 L93:
02A6 8C2D mov R24,R12
02A8 8038 cpi R24,128
02AA 71F0 breq L85
02AC X36:
02AC 8138 cpi R24,129
02AE 79F0 breq L86
02B0 X37:
02B0 25C0 xjmp L81
02B2 L94:
02B2 8C2D mov R24,R12
02B4 8839 cpi R24,152
02B6 B9F0 breq L90
02B8 X38:
02B8 8839 cpi R24,152
02BA 00F1 brlo L81
02BC X39:
02BC L95:
02BC 8C2D mov R24,R12
02BE 8E39 cpi R24,158
02C0 B1F0 breq L91
02C2 X40:
02C2 8F39 cpi R24,159
02C4 C1F0 breq L92
02C6 X41:
02C6 1AC0 xjmp L81
02C8 L85:
02C8 .dbline 264
02C8 ; {
02C8 ; case PARAM_BUILD_NUMBER_LOW:
02C8 ; tmp = CONFIG_PARAM_BUILD_NUMBER_LOW;
02C8 0024 clr R0
02CA 0A8A std y+18,R0
02CC .dbline 265
02CC ; break;
02CC 17C0 xjmp L82
02CE L86:
02CE .dbline 267
02CE ; case PARAM_BUILD_NUMBER_HIGH:
02CE ; tmp = CONFIG_PARAM_BUILD_NUMBER_HIGH;
02CE 0024 clr R0
02D0 0A8A std y+18,R0
02D2 .dbline 268
02D2 ; break;
02D2 14C0 xjmp L82
02D4 L87:
02D4 .dbline 270
02D4 ; case PARAM_HW_VER:
02D4 ; tmp = CONFIG_PARAM_HW_VER;
02D4 8FE0 ldi R24,15
02D6 8A8B std y+18,R24
02D8 .dbline 271
02D8 ; break;
02D8 11C0 xjmp L82
02DA L88:
02DA .dbline 273
02DA ; case PARAM_SW_MAJOR:
02DA ; tmp = CONFIG_PARAM_SW_MAJOR;
02DA 82E0 ldi R24,2
02DC 8A8B std y+18,R24
02DE .dbline 274
02DE ; break;
02DE 0EC0 xjmp L82
02E0 L89:
02E0 .dbline 276
02E0 ; case PARAM_SW_MINOR:
02E0 ; tmp = CONFIG_PARAM_SW_MINOR;
02E0 8AE0 ldi R24,10
02E2 8A8B std y+18,R24
02E4 .dbline 277
02E4 ; break;
02E4 0BC0 xjmp L82
02E6 L90:
02E6 .dbline 279
02E6 ; case PARAM_SCK_DURATION:
02E6 ; tmp = clock_speed;
02E6 20900700 lds R2,_clock_speed
02EA 2A8A std y+18,R2
02EC .dbline 280
02EC ; break;
02EC 07C0 xjmp L82
02EE L91:
02EE .dbline 282
02EE ; case PARAM_RESET_POLARITY:
02EE ; tmp = reset_polarity;
02EE 20900600 lds R2,_reset_polarity
02F2 2A8A std y+18,R2
02F4 .dbline 283
02F4 ; break;
02F4 03C0 xjmp L82
02F6 L92:
02F6 .dbline 285
02F6 ; case PARAM_CONTROLLER_INIT:
02F6 ; tmp = param_controller_init;
02F6 20900500 lds R2,_param_controller_init
02FA 2A8A std y+18,R2
02FC .dbline 286
02FC ; break;
02FC L81:
02FC L82:
02FC .dbline 289
02FC ; }
02FC ;
02FC ; num_bytes = 3;
02FC 83E0 ldi R24,3
02FE 90E0 ldi R25,0
0300 5C01 movw R10,R24
0302 .dbline 290
0302 ; msg_buffer[0] = CMD_GET_PARAMETER;
0302 80930800 sts _msg_buffer,R24
0306 .dbline 291
0306 ; msg_buffer[1] = STATUS_CMD_OK;
0306 2224 clr R2
0308 20920900 sts _msg_buffer+1,R2
030C .dbline 292
030C ; msg_buffer[2] = tmp;
030C 0A88 ldd R0,y+18
030E 00920A00 sts _msg_buffer+2,R0
0312 .dbline 293
0312 ; }
0312 51C7 xjmp L80
0314 L79:
0314 .dbline 297
0314 ; //////////////////////////////////////
0314 ; //CMD_LOAD_ADDRESS
0314 ; //////////////////////////////////////
0314 ; else if (cmd==CMD_LOAD_ADDRESS)
0314 8A85 ldd R24,y+10
0316 8630 cpi R24,6
0318 09F0 breq X140
031A 69C0 xjmp L98
031C X140:
031C X42:
031C .dbline 298
031C ; {
031C .dbline 299
031C ; address = ((unsigned long)msg_buffer[1])<<24;
031C 88E1 ldi R24,24
031E 90E0 ldi R25,0
0320 00910900 lds R16,_msg_buffer+1
0324 1127 clr R17
0326 2227 clr R18
0328 3327 clr R19
032A 8A93 st -y,R24
032C 0E940000 xcall lsl32
0330 10930100 sts _address+1,R17
0334 00930000 sts _address,R16
0338 30930300 sts _address+2+1,R19
033C 20930200 sts _address+2,R18
0340 .dbline 300
0340 ; address |= ((unsigned long)msg_buffer[2])<<16;
0340 20900A00 lds R2,_msg_buffer+2
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