📄 7113data.h
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#ifndef __SAA7113DATA_H__
#define __SAA7113DATA_H__
//#include "Camdef.h"
//#include "camif.h"
typedef struct samsung_t{ unsigned char subaddr; unsigned char value;
} SAA7113;
SAA7113 SAA7113_ITU656[] = {
//0x00 #Read only , chip version
{0x01,0x08}, //Recommended value
{0x02,0xc0}, //Amplifier plus anti-alias filter active & mode 0:cvbs from AL1
{0x03,0x33}, //Recommended value
{0x04,0x00}, //Gain control analog:channel 1 value: 256
{0x05,0x00}, //Gain control analog:channel 2 value: 256
{0x06,0xe9}, //Horizontal sync begin:Recommended value
{0x07,0x0d}, //Horizontal sync stop:Recommended value
{0x08,0x98}, //Sync control
{0x09,0x01}, //Luminance control
{0x0a,0x80}, //Luminance brightness control
{0x0b,0x47}, //Luminance contrast control
{0x0c,0x40}, //Chrominance saturation control
{0x0d,0x00}, //Chrominance hue control
{0x0e,0x01}, //Chrominance control:PAL,comb filter on, normal
{0x0f,0x2a}, //Chrominance gain control
{0x10,0x00}, //Format/delay control,VREF pulse position and length VRLN,Fine position of HS,Output format selection
{0x11,0x0c}, //Output control 1
{0x12,0x01}, //RTS1 output control , RTS0 output control
{0x13,0x00}, //Output control
{0x14,0x00}, //reserved
{0x15,0x00}, //VGATE start
{0x16,0x00}, //VGATE stop
{0x17,0x00}, //MSBs for VGATE control
{0x18,0x00}, //reserved :18H to 1eH
{0x19,0x00},
{0x1a,0x00},
{0x1b,0x00},
{0x1c,0x00},
{0x1d,0x00},
{0x1e,0x00},
//0x1f #Read only
{0x20,0x00}, //reserved :20 to 3fH
{0x21,0x00},
{0x22,0x00},
{0x23,0x00},
{0x24,0x00},
{0x25,0x00},
{0x26,0x00},
{0x27,0x00},
{0x28,0x00},
{0x29,0x00},
{0x2a,0x00},
{0x2b,0x00},
{0x2c,0x00},
{0x2d,0x00},
{0x2e,0x00},
{0x2f,0x00},
{0x30,0x00},
{0x31,0x00},
{0x32,0x00},
{0x33,0x00},
{0x34,0x00},
{0x35,0x00},
{0x36,0x00},
{0x37,0x00},
{0x38,0x00},
{0x39,0x00},
{0x3a,0x00},
{0x3b,0x00},
{0x3c,0x00},
{0x3d,0x00},
{0x3f,0x00},
{0x40,0x02}, //slicer control
{0x41,0xff}, //LCR register: 41H TO 57H ,default value 0xff
{0x42,0xff},
{0x43,0xff},
{0x44,0xff},
{0x45,0xff},
{0x46,0xff},
{0x47,0xff},
{0x48,0xff},
{0x49,0xff},
{0x4a,0xff},
{0x4b,0xff},
{0x4c,0xff},
{0x4d,0xff},
{0x4e,0xff},
{0x4f,0xff},
{0x51,0xff},
{0x52,0xff},
{0x53,0xff},
{0x54,0xff},
{0x57,0xff},
{0x58,0x00}, //Framing code for programmable data types ??
{0x59,0x54}, //Horizontal offset #Recommended value
{0x5a,0x07}, //Vertical offset: Value for 50 Hz 625 lines input
{0x5b,0x83}, //field offset and MSBs for horizontal and vertical offset
{0x5c,0x00}, //reserved
{0x5d,0x00}, //reserved
{0x5e,0x00}, //sliced data identification code #default value
{0x5f,0x00},
//0x60,Slicer status bits # read only
//0x61,Slicer status bits # read only
//0x62,Slicer status bits # read only
//All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
/*
{0x00,0x08}, //Read only , Recommended value
{0xc0,0x33}, //Amplifier plus anti-alias filter active & mode 0:cvbs from al11 , Recommended value
{0x00,0x00}, //Gain control value: 256
{0xe9,0x0d}, //Horizontal sync begin:Recommended value , Horizontal sync stop:Recommended value
{0x98,0x01}, //Sync control , Luminance control
{0x80,0x47}, //Luminance brightness control , Luminance contrast control
{0x40,0x00}, //Chrominance saturation control , Chrominance hue control
{0x01,0x2a}, //Chrominance control:PAL,comb filter on,normal , Chrominance gain control ?
{0x00,0x0c}, //
{0x01,0x00}, //default
{0x00,0x00}, //non-wideo
{0x00,0x00},
{0x00,0x00}, //reserved,read only
{0x00,0x00}, //the following 32 registers are reserved
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00}, //the 16th
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x00,0x00},
{0x02,0xff}, //slicer control1,the following 23 registers are all oxff
{0xff,0xff},
{0xff,0xff},
{0xff,0xff}, //the 7th
{0xff,0xff},
{0xff,0xff},
{0xff,0xff},
{0xff,0xff},
{0xff,0xff},
{0xff,0xff},
{0xff,0xff},
{0xff,0xff},
{0x00,0x54}, //
{0x07,0x83},
{0x00,0x00}, //these 2 reserved
{0x00,0x00},
//All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
//there are still 3 registers.each of the 3 is read only
*/
};
#define SAA7113_INIT_REGS (sizeof(SAA7113_ITU656)/sizeof(SAA7113_ITU656[0]))
#endif /*__SAA7113DATA_H__ */
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