user_face.h

TI DSP 5410烧写SST400A的程序代码

//filename: user_face.h
/* Register Definition  MCBSP  */

#define SPSA_ADDR(port)  	  (port ? 0x48 : 0x38)
#define SPSD_ADDR(port)  	  (port ? 0x49 : 0x39)

#define DRR2_ADDR(port)  	  (port ? 0x40 : 0x20)
#define DRR1_ADDR(port)  	  (port ? 0x41 : 0x21)
#define DXR2_ADDR(port)  	  (port ? 0x42 : 0x22)
#define DXR1_ADDR(port)  	  (port ? 0x43 : 0x23)

#define MCBSP_ACCSUB_ADDR(port) (port ? 0x49 : 0x39)

#define SPCR1_SUBADDR	0x00
#define SPCR2_SUBADDR	0x01
#define RCR1_SUBADDR	0x02
#define RCR2_SUBADDR    0x03
#define XCR1_SUBADDR 	0x04
#define XCR2_SUBADDR    0x05
#define SRGR1_SUBADDR	0x06
#define SRGR2_SUBADDR	0x07
#define MCR1_SUBADDR    0x08
#define MCR2_SUBADDR    0x09
#define RCERA_SUBADDR	0x0A
#define RCERB_SUBADDR	0x0B
#define XCERA_SUBADDR	0x0C
#define XCERB_SUBADDR	0x0D
#define PCR_SUBADDR	    0x0E

/*
VC5402----------McBSP0	McBSP1		
Name	Address	Name	Address	Sub-Address	Description
SPCR10 	39h	SPCR11 	49h	00h	Serial port control register 1
SPCR20 	39h	SPCR21 	49h	01h	Serial port control register 2
RCR10 	39h	RCR11 	49h	02h	Receive control register 1
RCR20 	39h	RCR21 	49h	03h	Receive control register 2
XCR10 	39h	XCR11 	49h	04h	Transmit control register 1
XCR20 	39h	XCR21 	49h	05h	Transmit control register 2
SRGR10 	39h	SRGR11 	49h	06h	Sample rate generator register 1
SRGR20 	39h	SRGR21 	49h	07h	Sample rate generator register 2
MCR10 	39h	MCR11 	49h	08h	Multichannel register 1
MCR20 	39h	MCR21 	49h	09h	Multichannel register 2
RCERA0 	39h	RCERA1 	49h	0Ah	Receive channel enable register partition A
RCERB0 	39h	RCERB1 	49h	0Bh	Receive channel enable register partition B
XCERA0 	39h	XCERA1 	49h	0Ch	Transmit channel enable register partition A
XCERB0 	39h	XCERB1 	49h	0Dh	Transmit channel enable register partition B
PCR0 	39h	PCR1 	49h	0Eh	Pin control register
*/
//SPCR10 	39h	SPCR11 	49h	00h	Serial port control register 1
#define   	bsp_SPCR10		0x0000
//SPCR20 	39h	SPCR21 	49h	01h	Serial port control register 2
#define 	bsp_SPCR20		0x0200     // enable Free-running model;
//PCR0 	    39h	PCR1 	49h	0Eh	Pin control register
#define		bsp_PCR0		0x000C     // FSXP bit =1,FSRP bit=1;
//RCR10 	39h	RCR11 	49h	02h	Receive control register 1
#define 	bsp_RCR10		0x0040         
//RCR20 	39h	RCR21 	49h	03h	Receive control register 2
#define		bsp_RCR20		0x0044
//XCR10 	39h	XCR11 	49h	04h	Transmit control register 1
#define		bsp_XCR10		0x0040
//XCR20 	39h	XCR21 	49h	05h	Transmit control register 2
#define		bsp_XCR20		0x0044
//SRGR10 	39h	SRGR11 	49h	06h	Sample rate generator register 1
#define		bsp_SRGR10		0x0000
//SRGR20 	39h	SRGR21 	49h	07h	Sample rate generator register 2
#define 	bsp_SRGR20		0x0000
//MCR10 	39h	MCR11 	49h	08h	Multichannel register 1
#define		bsp_MCR10		0x0000
//MCR20 	39h	MCR21 	49h	09h	Multichannel register 2
#define 	bsp_MCR20		0x0000
//RCERA0 	39h	RCERA1 	49h	0Ah	Receive channel enable register partition A
//#define		RCERA1
//RCERB0 	39h	RCERB1 	49h	0Bh	Receive channel enable register partition B
//#define		RCERB1
//XCERA0 	39h	XCERA1 	49h	0Ch	Transmit channel enable register partition A
//#define		XCERA1	
//XCERB0 	39h	XCERB1 	49h	0Dh	Transmit channel enable register partition B
//#define		XCERB1

/*
Name	Address	Type	Description
DRR20 	20h	McBSP #0	McBSP0 data receive register 2
DRR10 	21h	McBSP #0	McBSP0 data receive register 1
DXR20 	22h	McBSP #0	McBSP0 data transmit register 2
DXR10 	23h	McBSP #0	McBSP0 data transmit register 1
DRR21 	40h	McBSP #1	McBSP1 data receive register 2
DRR11 	41h	McBSP #1	McBSP1 data receive register 1
DXR21 	42h	McBSP #1	McBSP1 data transmit register 2
DXR11 	43h	McBSP #1	McBSP1 data transmit register 1
*/
/*
SPSA0 	38h	McBSP #0	McBSP0 subbank address register
SPSD0 	39h	McBSP #0	McBSP0 subbank data register
SPSA1 	48h	McBSP #1	McBSP1 subbank address  register
SPSD1 	49h	McBSP #1	McBSP1 subbank data register
*/
//---------CPU  -----------
//ST1 	addr:0x0007	Status register 1  ST1[13]=XF
#define     ST0		    0x0006
#define     ST1			0x4007    //原来为0x0007,因c
#define  	PMST		0x001D
#define  	SWWSR		0x0028
#define  	SWCR		0x002B
#define  	BSCR		0x0029
#define 	CLKMD		0x0058
#define     DMPREC      0x0054

#define PMST_VAL        0x0020     //interupt vectors from ox80  
#define SWWSR_VAL       0x7FFF     // PMST中的TPTR位与中断向量表的起始地址有关； 
#define SWCR_VAL        0x0000  
#define BSCR_VAL        0x8802
#define CLKMD_VAL		0x0287
#define ST0_VAL         0x0000
#define ST1_VAL         0x0800
#define DMPREC_VAL      0xff3f