📄 timing_recovery_1.mdl
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DstBlock "P1"
DstPort 1
}
}
Line {
SrcBlock "Demux"
SrcPort 1
Points [55, 0; 0, -25]
DstBlock "P1"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "P2"
DstPort 2
}
Line {
SrcBlock "Sum2"
SrcPort 1
DstBlock "P3"
DstPort 2
}
Line {
SrcBlock "Demux"
SrcPort 2
Points [150, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "P1"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 3
Points [255, 0]
DstBlock "Sum2"
DstPort 2
}
Line {
SrcBlock "Demux"
SrcPort 4
Points [365, 0]
DstBlock "Sum3"
DstPort 2
}
Line {
SrcBlock "Sum3"
SrcPort 1
DstBlock "Yout"
DstPort 1
}
Annotation {
Name "Horner's Rule"
Position [348, 18]
}
Annotation {
Name "Filter Coefficients from Chris Dick Xilinx, \nor H. Meyer pp 520 (9-33) Digital Communications Receivers"
Position [157, 201]
}
}
}
Block {
BlockType Outport
Name "Yout"
Position [405, 118, 435, 132]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Line {
SrcBlock "Filter State"
SrcPort 1
DstBlock "MADS"
DstPort 1
}
Line {
SrcBlock "Xin"
SrcPort 1
DstBlock "Filter State"
DstPort 1
}
Line {
SrcBlock "Mu"
SrcPort 1
DstBlock "MADS"
DstPort 2
}
Line {
SrcBlock "MADS"
SrcPort 1
DstBlock "Yout"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "I/Q"
Ports [1, 1]
Position [760, 345, 820, 375]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Port {
PortNumber 1
Name "I/Q Data"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
System {
Name "I/Q"
Location [857, 657, 1193, 783]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "cmplx"
Position [15, 43, 45, 57]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType ComplexToRealImag
Name "Complex to\nReal-Imag"
Ports [1, 2]
Position [100, 29, 130, 71]
Output "Real and imag"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [220, 34, 255, 66]
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "2"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
reset_popup "None"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1]
Position [175, 31, 180, 69]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Outport
Name "2x real"
Position [275, 43, 305, 57]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Line {
SrcBlock "Complex to\nReal-Imag"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Complex to\nReal-Imag"
SrcPort 2
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "cmplx"
SrcPort 1
DstBlock "Complex to\nReal-Imag"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Delay1"
DstPort 1
}
Line {
SrcBlock "Delay1"
SrcPort 1
DstBlock "2x real"
DstPort 1
}
Annotation {
Name "to visually allign traces"
Position [237, 86]
}
}
}
Block {
BlockType ZeroOrderHold
Name "Primary Rx Sampler\n (I/Q ADC)"
Position [70, 231, 135, 289]
SampleTime "1/(D*Fsymbol)"
}
Block {
BlockType Reference
Name "RRC with D=2"
Ports [1, 1]
Position [170, 229, 235, 291]
DialogController "dspdialog.FIRDecimation"
DialogControllerArgs "DataTag0"
SourceBlock "dspmlti4/FIR\nDecimation"
SourceType "FIR Decimation"
h "rrc_coef"
D "2"
filtStruct "Direct form"
framing "Maintain input frame size"
outputBufInitCond "0"
additionalParams off
allowOverrides on
firstCoeffMode "Same word length as input"
firstCoeffWordLength "16"
firstCoeffFracLength "15"
outputMode "Same as accumulator"
outputWordLength "16"
outputFracLength "15"
accumMode "Inherit via internal rule"
accumWordLength "32"
accumFracLength "30"
prodOutputMode "Inherit via internal rule"
prodOutputWordLength "32"
prodOutputFracLength "30"
roundingMode "Floor"
overflowMode off
LockScale off
FilterSource "Specify via dialog"
FilterObject "Hm_firdecim"
}
Block {
BlockType Scope
Name "Symbol Clocks\nand Data"
Ports [3]
Position [915, 136, 965, 244]
Floating off
Location [9, 52, 248, 304]
Open on
NumInputPorts "3"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
TimeRange "2e-006"
YMin "-0.1~-0.1~-1.5"
YMax "1.1~1.1~1.5"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Reference
Name "Symbol Freq\n% Error "
Ports [1, 1]
Position [145, 50, 175, 80]
BackgroundColor "yellow"
SourceBlock "simulink/Math\nOperations/Slider\nGain"
SourceType "Slider Gain"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
low "-1.5"
gain "0"
high "1.5"
}
Block {
BlockType SubSystem
Name "Symbol Sampling with\nOptional Carrier Recovery"
Ports [3, 2]
Position [450, 380, 555, 480]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
System {
Name "Symbol Sampling with\nOptional Carrier Recovery"
Location [133, 288, 668, 580]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "Symbol Clock"
Position [25, 38, 55, 52]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Inport
Name "Data"
Position [25, 98, 55, 112]
Port "2"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Inport
Name "Rec_ON"
Position [65, 123, 95, 137]
Port "3"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [115, 29, 150, 61]
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "2"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
reset_popup "None"
}
Block {
BlockType SubSystem
Name "Symbol Sampler1"
Ports [2, 1, 1]
Position [150, 90, 315, 145]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
System {
Name "Symbol Sampler1"
Location [31, 286, 569, 551]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [45, 198, 75, 212]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Inport
Name "Carrier Recovery ON"
Position [40, 28, 70, 42]
Port "2"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [165, 65, 185, 85]
}
Block {
BlockType SubSystem
Name "Carrier Recovery"
Ports [1, 1, 1]
Position [170, 117, 305, 173]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
System {
Name "Carrier Recovery"
Location [61, 144, 996, 601]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "I/Q In"
Position [25, 113, 55, 127]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [110, 60, 130, 80]
}
Block {
BlockType Reference
Name "Break Loop"
Ports [2, 1]
Position [105, 172, 135, 208]
SourceBlock "simulink/Signal\nRouting/Manual Switch"
SourceType "Manual Switch"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
sw "0"
action "0"
varsize off
}
Block {
BlockType Scope
Name "Carrier Recovery Signals"
Ports [2]
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