register.h

SMDK6410 Test Code Revision 02. s3c6410 official test code, shifting all the controller functional

#define FGTU_TEX6_L4_OFFSET      (FIMG_BASE+0x601FC)
#define FGTU_TEX6_L5_OFFSET      (FIMG_BASE+0x60200)
#define FGTU_TEX6_L6_OFFSET      (FIMG_BASE+0x60204)
#define FGTU_TEX6_L7_OFFSET      (FIMG_BASE+0x60208)
#define FGTU_TEX6_L8_OFFSET      (FIMG_BASE+0x6020C)
#define FGTU_TEX6_L9_OFFSET      (FIMG_BASE+0x60210)
#define FGTU_TEX6_L10_OFFSET     (FIMG_BASE+0x60214)
#define FGTU_TEX6_L11_OFFSET     (FIMG_BASE+0x60218)
#define FGTU_TEX6_MIN_LEVEL      (FIMG_BASE+0x6021C)
#define FGTU_TEX6_MAX_LEVEL      (FIMG_BASE+0x60220)
#define FGTU_TEX6_BASE_ADDR      (FIMG_BASE+0x60224)
#define FGTU_TEX7_CTRL           (FIMG_BASE+0x60230)
#define FGTU_TEX7_USIZE          (FIMG_BASE+0x60234)
#define FGTU_TEX7_VSIZE          (FIMG_BASE+0x60238)
#define FGTU_TEX7_PSIZE          (FIMG_BASE+0x6023C)
#define FGTU_TEX7_L1_OFFSET      (FIMG_BASE+0x60240)
#define FGTU_TEX7_L2_OFFSET      (FIMG_BASE+0x60244)
#define FGTU_TEX7_L3_OFFSET      (FIMG_BASE+0x60248)
#define FGTU_TEX7_L4_OFFSET      (FIMG_BASE+0x6024C)
#define FGTU_TEX7_L5_OFFSET      (FIMG_BASE+0x60250)
#define FGTU_TEX7_L6_OFFSET      (FIMG_BASE+0x60254)
#define FGTU_TEX7_L7_OFFSET      (FIMG_BASE+0x60258)
#define FGTU_TEX7_L8_OFFSET      (FIMG_BASE+0x6025C)
#define FGTU_TEX7_L9_OFFSET      (FIMG_BASE+0x60260)
#define FGTU_TEX7_L10_OFFSET     (FIMG_BASE+0x60264)
#define FGTU_TEX7_L11_OFFSET     (FIMG_BASE+0x60268)
#define FGTU_TEX7_MIN_LEVEL      (FIMG_BASE+0x6026C)
#define FGTU_TEX7_MAX_LEVEL      (FIMG_BASE+0x60270)
#define FGTU_TEX7_BASE_ADDR      (FIMG_BASE+0x60274)
#define FGTU_COLOR_KEY1 		 (FIMG_BASE+0x60280) /* R/W Color Key1 */
#define FGTU_COLOR_KEY2 		 (FIMG_BASE+0x60284) /* R/W Color Key2 */
#define FGTU_COLOR_KEY_YUV 		 (FIMG_BASE+0x60288) /* R/W YUV Color Key */
#define FGTU_COLOR_KEY_MASK 	 (FIMG_BASE+0x6028C) /* R/W Color Key Mask */
/* R/W Palette address for indexed texture */
#define FGTU_PALETTE_ADDR 	     (FIMG_BASE+0x60290)
/* R/W Palette entry point */
#define FGTU_PALETTE_ENTRY 	     (FIMG_BASE+0x60294)

/* R/W Vertex texture n’s control */
#define FGTU_VTXTEX0_CTRL 		 (FIMG_BASE+0x602C0)
/* R/W Vertex texture base level */
#define FGTU_VTXTEX0_BASE_ADDR 	 (FIMG_BASE+0x602C4)
#define FGTU_VTXTEX1_CTRL 		 (FIMG_BASE+0x602C8)
#define FGTU_VTXTEX1_BASE_ADDR 	 (FIMG_BASE+0x602CC)
#define FGTU_VTXTEX2_CTRL 		 (FIMG_BASE+0x602D0)
#define FGTU_VTXTEX2_BASE_ADDR 	 (FIMG_BASE+0x602D4)
#define FGTU_VTXTEX3_CTRL 		 (FIMG_BASE+0x602D8)
#define FGTU_VTXTEX3_BASE_ADDR 	 (FIMG_BASE+0x602DC)

#define FGL_MIN_TEXTURE_WIDTH	    1
#define FGL_MIN_TEXTURE_HEIGHT	    1
#define FGL_MIN_TEXTURE_DEPTH	    1
#define FGL_MAX_TEXTURE_WIDTH	    2048
#define FGL_MAX_TEXTURE_HEIGHT	    2048
#define FGL_MAX_TEXTURE_DEPTH	    2048
#define FGL_MAX_TEXTURE_UNITS       8

/// Texture Unit Definitions
#define MAXVALUE_TU_TEX_SIZE		((1 << 11) - 1)

#define BITINTERVAL_TU_UNIT			(0x50)
#define MAXVALUE_TU_UNIT			(0x7)
#define MAXVALUE_TU_MIPMAP_LEVEL	(11)

#define MAXVALUE_TU_CK_UNIT			1
#define BITSHIFT_TU_CK_RED			16
#define BITSHIFT_TU_CK_GREEN		8

#define MAXVALUE_TU_CK_MASK			7
#define MAXVALUE_TU_PAL_ADDR		255

#define BITSHIFT_TU_VTX_UMODE		10
#define BITSHIFT_TU_VTX_VMODE		8
#define BITSHIFT_TU_VTX_USIZE		4


/*****************************************************************************
	PER-FRAGMENT REGISTER
 *****************************************************************************/
/* R/W 	Scissor X coordinate */
#define FGPF_SCISSOR_XCORD		(FIMG_BASE+0x70000)
/* R/W 	Scissor Y coordinate */
#define FGPF_SCISSOR_YCORD		(FIMG_BASE+0x70004)
/* R/W 	Alpha test */
#define FGPF_ALPHA       		(FIMG_BASE+0x70008)
/* R/W 	Frontface stencil */
#define FGPF_FRONTFACE_STENCIL 	(FIMG_BASE+0x7000C)
/* R/W 	Backface stencil  */
#define FGPF_BACKFACE_STENCIL 	(FIMG_BASE+0x70010)
/* R/W 	Depth test  */
#define FGPF_DEPTH       		(FIMG_BASE+0x70014)
/* R/W 	Constant color for Blending  */
#define FGPF_BLEND_COLOR		(FIMG_BASE+0x70018)
/* R/W 	Blending  */
#define FGPF_BLEND 				(FIMG_BASE+0x7001C)
/* R/W 	RGBA color logical operation  */
#define FGPF_LOGIC_OP 			(FIMG_BASE+0x70020)
/* R/W 	Color buffer write mask  */
#define FGPF_COLOR_MASK 		(FIMG_BASE+0x70024)
/* R/W 	Depth buffer write mask  */
#define FGPF_STENCIL_DEPTH_MASK (FIMG_BASE+0x70028)
/* R/W 	Color buffer control */
#define FGPF_COLORBUF_CTRL 		(FIMG_BASE+0x7002C)
/* R/W 	Depth buffer base address */
#define FGPF_DEPTHBUF_ADDR		(FIMG_BASE+0x70030)
/* R/W 	Frame buffer base address */
#define FGPF_COLORBUF_ADDR 	    (FIMG_BASE+0x70034)
/* R/W 	Frame buffer width */
#define FGPF_COLORBUF_WIDTH 	(FIMG_BASE+0x70038)

#define FGPF_FB_MAX_STRIDE      2048

#define COLOR_MASK_ALPHA		0x00000001
#define COLOR_MASK_RED			0x00000002
#define COLOR_MASK_GREEN		0x00000004
#define COLOR_MASK_BLUE			0x00000008
#define DEPTH_MAX_VALUE		    0xFFFFFF
#define DEPTH_MIN_VALUE		    0x0
#define DEPTH_ENABLE_MASK		0x1
#define STENCIL_ENABLE_MASK     0x1



#ifdef _FIMG3DSE_VER_1_2
/*****************************************************************************
	DMA CONTROL REGISTER
 *****************************************************************************/
	/* R/W DMA proority control 0000_0000h */
    #define FIMG_DMA_CNTL0          (FIMG_BASE+0x80000)
    #define FIMG_DMA_CNTL1          (FIMG_BASE+0x80004)
    #define FIMG_DMA_CNTL2          (FIMG_BASE+0x80008)
#endif

/*****************************************************************************
	GLOBAL REGISTER
 *****************************************************************************/
/* W  	Each block's reset signal 				FFFF_FFFFh*/
//#define FIMG_GLOBREG_SWRESET 			0x00000000
//#define SW_RESET_VS					0x00000001
//#define SW_RESET_RESERVED0			0x0000000E
//#define SW_RESET_VSMASK				0x0000000F
//#define SW_RESET_PE					0x00000010
//#define SW_RESET_RESERVED1			0x000000E0
//#define SW_RESET_RE					0x00000100
//#define SW_RESET_RESERVED2			0x00000E00
//#define SW_RESET_PS					0x00001000
//#define SW_RESET_RESERVED3			0x0000E000
//#define SW_RESET_PF					0x00010000
//#define SW_RESET_RESERVED4			0xFFFE0000
#define SW_RESET_ALL				0x00011111


/*****************************************************************************
	HOST INTERFACE REGISTER
 *****************************************************************************/
//#define FIMG_HISFR_PRIMITIVE 				0x08000	/* r/W 	Primitive's sort */
#define PRIMITIVE_CLRMASK 			0xFFFFFFF0
#define PRIMITIVE_TRIANGLE 			0x00000001
#define PRIMITIVE_TRIANGLESTRIP 	0x00000002
#define PRIMITIVE_TRIANGLEFAN 		0x00000003

/* r/W 	Vertex's format refer to geometry		*/
//#define FIMG_HISFR_VF0 					0x08004
/* r/W 	Vertex's format refer to texture		*/
//#define FIMG_HISFR_VF1 					0x08008
#define VERTEX_FORMAT_X				0x8
#define VERTEX_FORMAT_XY			0x9
#define VERTEX_FORMAT_XYZ			0xA
#define VERTEX_FORMAT_XYZW			0xB

/* r/W 	Vertex's data type refer to geometry	*/
//#define FIMG_HISFR_VFT0 					0x0800C
/* r/W 	Vertex's data type refer to texture		*/
//#define FIMG_HISFR_VFT1 					0x08010
#define VTX_DATATYPE_BYTE			0x0
#define VTX_DATATYPE_SHORT			0x1
#define VTX_DATATYPE_INT			0x2
#define VTX_DATATYPE_FLOAT			0x3
#define VTX_DATATYPE_UBYTE			0x4
#define VTX_DATATYPE_USHORT			0x5
#define VTX_DATATYPE_UINT			0x6
#define VTX_DATATYPE_FIXED			0x7
#define VTX_DATATYPE_NORMAL_BYTE	0x8
#define VTX_DATATYPE_NORMAL_SHORT	0x9
#define VTX_DATATYPE_NORMAL_INT		0xA
#define VTX_DATATYPE_NORMAL_UBYTE	0xC
#define VTX_DATATYPE_NORMAL_USHORT	0xD
#define VTX_DATATYPE_NORMAL_UINT	0xE
#define VTX_DATATYPE_NORMAL_FIXED	0xF

/*****************************************************************************
 *	TEXTURE CONTROL REGISTER FELID DEFINE
 *****************************************************************************/
#define TEXCTRL_TEXTURE_TYPE_SHIFT       27
#define TEXCTRL_COLOR_KEY_SHIFT          21
#define TEXCTRL_EXPANSION_SHIFT          20
#define TEXCTRL_PALETTE_FORMAT_SHIFT     17
#define TEXCTRL_TEXTURE_FORMAT_SHIFT     12
#define TEXCTRL_U_WRAPMODE_SHIFT         10
#define TEXCTRL_V_WRAPMODE_SHIFT         8
#define TEXCTRL_P_WRAPMODE_SHIFT         6
#define TEXCTRL_NONPARAMETRIC_SHIFT      4
#define TEXCTRL_MAG_FILTER_SHIFT         3
#define TEXCTRL_MIN_FILTER_SHIFT         2
#define TEXCTRL_MIPMAP_FILTER_SHIFT      0

/*****************************************************************************
	PER-FRAGMENT REGISTER FELID DEFINE
 *****************************************************************************/
#define SCISSOR_MAX_SIZE		        (2048)


/*****************************************************************************
	PROBE WATCH POINTS FOR FIMG-3DSE V1.X
 *****************************************************************************/
#define FGWP_DEBUG_ENABLE 	(FIMG_BASE+0x200)  /* DebugOn           */
#define FGWP_IN_HI_GRP0 	(FIMG_BASE+0x204)  /* Watch_InHI_Grp0   */
#define FGWP_IN_HI_GRP1 	(FIMG_BASE+0x208)  /* Watch_InHI_Grp1   */
#define FGWP_IN_VC_VS 	    (FIMG_BASE+0x20C)  /* Watch_InVC_VS     */  
#define FGWP_IN_PE 	        (FIMG_BASE+0x210)  /* Watch_InPE        */
#define FGWP_IN_TSE_RA 	    (FIMG_BASE+0x214)  /* Watch_InTSE_RA    */
#define FGWP_IN_PS0 	    (FIMG_BASE+0x218)  /* Watch_InPS0       */      
#define FGWP_IN_PS1 	    (FIMG_BASE+0x21C)  /* Watch_InPS1       */  
#define FGWP_IN_VTU_TU 	    (FIMG_BASE+0x220)  /* Watch_InVTU_TU    */
#define FGWP_IN_TCACHE 	    (FIMG_BASE+0x224)  /* Watch_InTCache    */
#define FGWP_IN_PF 	        (FIMG_BASE+0x228)  /* Watch_InPF        */
#define FGWP_IN_CZCACHE 	(FIMG_BASE+0x22C)  /* Watch_InCZCache   */
#define FGWP_IN_AXIRB 	    (FIMG_BASE+0x230)  /* Watch_InAXIArb    */
#define FGWP_IN_DMA 	    (FIMG_BASE+0x234)  /* Watch_InDMA       */


/***********************************************************************
	@USAGE
	WRITE
		if you want to write SFR by 32-bits, then
			outw(SFR_ADDRESS, (unsigned int)WDATA);
		if by 16-bits, then
			outs(SFR_ADDRESS, (unsigned short int)WDATA);
		if by 8-bits, then
			outb(SFR_ADDRESS, (unsigned char)WDATA);
	READ
		if you read SFR by 32-bits, then
			(unsigned int)RDATA = inw(SFR_ADDRESS);
		if by 16-bits, then
			(unsigned short int)RDATA = ins(SFR_ADDRESS);
		if by 8-bits, then
			(unsigned char)RDATA = inb(SFR_ADDRESS);
*************************************************************************/

typedef volatile unsigned char 	*vbptr;
typedef volatile unsigned short *vsptr;
typedef volatile unsigned int 	*vwptr;
typedef volatile float			*vfptr;

#define READREGB(Port)		(*((vbptr) (Port)))
#define READREGPB(Port, Y)	(Y =*((vbptr) (Port)))
#define WRITEREGB(Port, X)	(*((vbptr) (Port)) = (unsigned char) (X))

#define READREGS(Port)		(*((vsptr) (Port)))
#define READREGPS(Port, Y)	(Y =*((vsptr) (Port)))
#define WRITEREGS(Port, X)	(*((vsptr) (Port)) = (unsigned short) (X))

#define READREG(Port)		(*((vwptr) (Port)))
#define READREGP(Port, Y)	(Y =*((vwptr) (Port)))
#define WRITEREG(Port, X)	(*((vwptr) (Port)) = (unsigned int) (X))

#define READREGF(Port)		(*((vfptr) (Port)))
#define READREGPF(Port, Y)	(Y =*((vfptr) (Port)))
#define WRITEREGF(Port, X)	(*((vfptr) (Port)) = (float) (X))

#ifdef __cplusplus
}
#endif


#endif /* __FIMG_3DREGS_H__ */

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