register.h

SMDK6410 Test Code Revision 02. s3c6410 official test code, shifting all the controller functional

/**
 * Samsung Project
 * Copyright (c) 2007 Mobile XG, Samsung Electronics, Inc.
 * All right reserved.
 *
 * This software is the confidential and proprietary information
 * of Samsung Electronics Inc. ("Confidential Information"). You
 * shall not disclose such Confidential Information and shall use
 * it only in accordance with the terms of the license agreement
 * you entered into with Samsung Electronics.
 */

/**
 * @file	register.h
 * @brief	This is the file that has definitions of the register map and etc.
 * @author	Cheolkyoo Kim
 * @version	1.5
 */

/**
 * 	@brief
 *		FIMGSE 3D Hardware Register Defines
 *		FG[GB]_xxxx : Global control/state
 *		FGHI_xxxx : Host Interface
 *		FGVS_xxxx : Vertex Shaders
 *		FGPE_xxxx : Primitive Engine (Clipping, Viewport-mapping, etc)
 *		FGRE_xxxx : Raster Engine (Setup, Rasterizer, etc)
 *		FGPS_xxxx : Pixel Shaders
 *		FGTU_xxxx : Texture Units
 *		FGPF_xxxx : Per-Fragment Units
 */
 
#if !defined(__FIMG_3DREGS_H__)
#define __FIMG_3DREGS_H__

#include "fglconfig.h"

#ifdef __cplusplus
extern "C" {
#endif

#define FIMG_BASE   		0x72000000


/*****************************************************************************************
 **     REGISTER NAME      	OFFSET            R/W  DESCRIPTION              INITIAL VALUE
 *****************************************************************************************/

/*****************************************************************************
 *	GLOBAL REGISTER
 *****************************************************************************/
/* R  	The status of pipeline	*/
#define FG_PIPELINE_STATUS	    (FIMG_BASE+0x0)
/* R/W 	Cache control register  */
#define FG_CACHE_CTRL		    (FIMG_BASE+0x4)
/* W 	Hwrdware blocks reset	FFFF_FFFFh */
#define FG_SW_RESET			    (FIMG_BASE+0x8)
/* R/W Interrupt pendign register 0000_0000h */
#define FG_INT_PENDING		    (FIMG_BASE+0x40)
/* R/W Enables of Disables interrupts.	0000_0000h */
#define FG_INT_MASK			    (FIMG_BASE+0x44)
/* R/W Specifies the blocks in FIMG-3DSE
 * which are candidates to generate interrupts.
 * 0000_0000h */
#define FG_PIPELINE_MASK	    (FIMG_BASE+0x48)
/* R/W Specifies the value of pipeline-state
 * when interrupts are to occur.	0000_0000h */
#define FG_PIPELINE_TARGET_STATE (FIMG_BASE+0x4C)
/* R 	Captures the first pipeline-state when several interrupts occur.
 * 0000_0000h */
#define FG_PIPELINE_INT_STATE	(FIMG_BASE+0x50)

/* R  	The status of pipeline	*/
#define FGGB_PIPESTATE		(FIMG_BASE+0x0)
/* R/W 	Cache control register  */
#define FGGB_CACHECTL		(FIMG_BASE+0x4)
/* W 	Hwrdware blocks reset	FFFF_FFFFh*/
#define FGGB_RST			(FIMG_BASE+0x8)
/* R 	Hwrdware version */
#define FGGB_VERSION			(FIMG_BASE+0x10)
/* R/W Interrupt pendign register 0000_0000h*/
#define FGGB_INTPENDING		(FIMG_BASE+0x40)
/* R/W Enables of Disables interrupts.	0000_0000h */
#define FGGB_INTMASK		(FIMG_BASE+0x44)
/* R/W Specifies the blocks in FIMG-3DSE
 * which are candidates to generate interrupts.	0000_0000h */
#define FGGB_PIPEMASK		(FIMG_BASE+0x48)
/* R/W Specifies the value of pipeline-state when interrupts are to occur.
 * 0000_0000h */
#define FGGB_PIPETGTSTATE	(FIMG_BASE+0x4C)
/* R 	Captures the first pipeline-state when several interrupts occur.
 * 0000_0000h */
#define FGGB_PIPEINTSTATE	(FIMG_BASE+0x50)



/*-----------------------------------------------------------------------------
 	Cache Control ( Vertex Texture, Texture, Color, Depth Cache )
 -----------------------------------------------------------------------------*/
#define	rFIMG_CACHE				(*(volatile unsigned *)FG_CACHE_CTRL)
#define BIT_ZCACHE0_FLUSH		(0x1)   	/// Depth cache flush
#define BIT_ZCACHE1_FLUSH		(0x1<<1)
#define BIT_CCACHE0_FLUSH		(0x1<<4)	/// Color cache flush
#define BIT_CCACHE1_FLUSH		(0x1<<5)
#define BIT_TCACHE0_CLEAR		(0x1<<8)	/// Texture cache flush
#define BIT_TCACHE1_CLEAR		(0x1<<9)
#define BIT_VTCACHE_CLEAR		(0x1<<12)	/// Vertex cache flush
#define BIT_CACHE_ALLMASK		(0x3fff)

/*****************************************************************************
 *	HOST INTERFACE REGISTER
 *****************************************************************************/
/* R   The num of empty slots of FIFO */
#define FGHI_FIFO_EMPTY_SPACE		(FIMG_BASE+0x8000)

	/* W	  The input port of FIFO */
#define FGHI_FIFO_ENTRY			(FIMG_BASE+0xC000)


/* R/W Host interface control */
#define FGHI_HI_CTRL				(FIMG_BASE+0x8008)
/* R/W Index offset register */
#define FGHI_IDX_OFFSET				(FIMG_BASE+0x800C)
/* R/W Destination address register of attribute to copy in VB */
#define FGHI_VTXBUF_ADDR			(FIMG_BASE+0x8010)
/* W   Entry point register of VB */
#define FGHI_VTXBUF_ENTRY   	    (FIMG_BASE+0xE000)

/* R/W Input attribute N control reg */
#define FGHI_ATTR0              	(FIMG_BASE+0x8040)
#define FGHI_ATTR1              	(FIMG_BASE+0x8044)
#define FGHI_ATTR2              	(FIMG_BASE+0x8048)
#define FGHI_ATTR3              	(FIMG_BASE+0x804C)
#define FGHI_ATTR4              	(FIMG_BASE+0x8050)
#define FGHI_ATTR5              	(FIMG_BASE+0x8054)
#define FGHI_ATTR6              	(FIMG_BASE+0x8058)
#define FGHI_ATTR7              	(FIMG_BASE+0x805C)
#define FGHI_ATTR8              	(FIMG_BASE+0x8060)
#define FGHI_ATTR9              	(FIMG_BASE+0x8064)
#define FGHI_ATTRA              	(FIMG_BASE+0x8068)
#define FGHI_ATTRB              	(FIMG_BASE+0x806C)
#define FGHI_ATTRC              	(FIMG_BASE+0x8070)
#define FGHI_ATTRD              	(FIMG_BASE+0x8074)
#define FGHI_ATTRE              	(FIMG_BASE+0x8078)
#define FGHI_ATTRF              	(FIMG_BASE+0x807C)

/* R/W Vertex buffer control of input attribute N */
#define FGHI_VTXBUF_CTRL0          (FIMG_BASE+0x8080)
#define FGHI_VTXBUF_CTRL1          (FIMG_BASE+0x8084)
#define FGHI_VTXBUF_CTRL2          (FIMG_BASE+0x8088)
#define FGHI_VTXBUF_CTRL3          (FIMG_BASE+0x808C)
#define FGHI_VTXBUF_CTRL4          (FIMG_BASE+0x8090)
#define FGHI_VTXBUF_CTRL5          (FIMG_BASE+0x8094)
#define FGHI_VTXBUF_CTRL6          (FIMG_BASE+0x8098)
#define FGHI_VTXBUF_CTRL7          (FIMG_BASE+0x809C)
#define FGHI_VTXBUF_CTRL8          (FIMG_BASE+0x80A0)
#define FGHI_VTXBUF_CTRL9          (FIMG_BASE+0x80A4)
#define FGHI_VTXBUF_CTRLA          (FIMG_BASE+0x80A8)
#define FGHI_VTXBUF_CTRLB          (FIMG_BASE+0x80AC)
#define FGHI_VTXBUF_CTRLC          (FIMG_BASE+0x80B0)
#define FGHI_VTXBUF_CTRLD          (FIMG_BASE+0x80B4)
#define FGHI_VTXBUF_CTRLE          (FIMG_BASE+0x80B8)
#define FGHI_VTXBUF_CTRLF          (FIMG_BASE+0x80BC)

/* R/W Vertex buffer base address of input attribute N */
#define FGHI_VTXBUF_BASE0          (FIMG_BASE+0x80C0)
#define FGHI_VTXBUF_BASE1          (FIMG_BASE+0x80C4)
#define FGHI_VTXBUF_BASE2          (FIMG_BASE+0x80C8)
#define FGHI_VTXBUF_BASE3          (FIMG_BASE+0x80CC)
#define FGHI_VTXBUF_BASE4          (FIMG_BASE+0x80D0)
#define FGHI_VTXBUF_BASE5          (FIMG_BASE+0x80D4)
#define FGHI_VTXBUF_BASE6          (FIMG_BASE+0x80D8)
#define FGHI_VTXBUF_BASE7          (FIMG_BASE+0x80DC)
#define FGHI_VTXBUF_BASE8          (FIMG_BASE+0x80E0)
#define FGHI_VTXBUF_BASE9          (FIMG_BASE+0x80E4)
#define FGHI_VTXBUF_BASEA          (FIMG_BASE+0x80E8)
#define FGHI_VTXBUF_BASEB          (FIMG_BASE+0x80EC)
#define FGHI_VTXBUF_BASEC          (FIMG_BASE+0x80F0)
#define FGHI_VTXBUF_BASED          (FIMG_BASE+0x80F4)
#define FGHI_VTXBUF_BASEE          (FIMG_BASE+0x80F8)
#define FGHI_VTXBUF_BASEF          (FIMG_BASE+0x80FC)


/*****************************************************************************
 *	VERTEX SHADER REGISTER
 *****************************************************************************/
/// Configuration Register
/* W   Configuration register of the vertex shader */
#define FGVS_CONFIG				(FIMG_BASE+0x1C800)
/* R   Internal status register */
#define FGVS_STATUS				(FIMG_BASE+0x1C804)
/* R/W Start and end address of the vertex shader program */
#define FGVS_PC_RANGE			(FIMG_BASE+0x20000)
/* R/W The number of attributes for the input and output registers*/
#define FGVS_ATTRIB_NUM			(FIMG_BASE+0x20004)
/* R/W Index of input attributes 0~3 */
#define FGVS_IN_ATTRIB_IDX0		(FIMG_BASE+0x20008)
/* R/W Index of input attributes 4~7 */
#define FGVS_IN_ATTRIB_IDX1		(FIMG_BASE+0x2000C)
/* R/W Index of input attributes 8~11 */
#define FGVS_IN_ATTRIB_IDX2		(FIMG_BASE+0x20010)
/* R/W Index of output attributes 0~3 */
#define FGVS_OUT_ATTRIB_IDX0	(FIMG_BASE+0x20014)
/* R/W Index of output attributes 4~7 */
#define FGVS_OUT_ATTRIB_IDX1	(FIMG_BASE+0x20018)
/* R/W Index of output attributes 8~11 */
#define FGVS_OUT_ATTRIB_IDX2	(FIMG_BASE+0x2001C)

/// Address Map of Vertex Shader
/* R/W Reseved[16KB] Actual[16KB] VS's instruction */
#define FGVS_INSTMEM_SADDR		(FIMG_BASE+0x10000)
/* R/W register */
#define FGVS_INSTMEM_EADDR		(FIMG_BASE+0x11FFF)
/* R/W Reseved[16KB] Actual[4KB] VS's constant float */
#define FGVS_CFLOAT_SADDR 		(FIMG_BASE+0x14000)
/* R/W register */
#define FGVS_CFLOAT_EADDR 		(FIMG_BASE+0x14FFF)
/* R/W Reseved[ 1KB] Actual[256B] VS's constant integer */
#define FGVS_CINT_SADDR 		(FIMG_BASE+0x18000)
/* R/W register */
#define FGVS_CINT_EADDR 		(FIMG_BASE+0x1803F)
/* R/W Reseved[ 1KB] Actual[4B] VS's Boolean register */
#define FGVS_CBOOL_SADDR 		(FIMG_BASE+0x18400)
#define FGVS_CBOOL_EADDR 		(FIMG_BASE+0x18400)

/*-----------------------------------------------------------------------------
  VERTEX SHADER FIELD
 -----------------------------------------------------------------------------*/
#define VSIN_ATTRIB_NUM_MASK    0x000F0000
#define VSIN_ATTRIB_MAX_SIZE    10
#define VSIN_ATTRIB_MIN_SIZE    1
#define VSOUT_ATTRIB_NUM_MASK   0x0000000F
#define VSOUT_ATTRIB_MAX_SIZE   10
#define VSOUT_ATTRIB_MIN_SIZE   1

//#define FGVS_INSTMEM_SIZE		0x2000 	/* 8*1024(Byte) = 2048(WORD) = 0x800(Hex) */
//#define FGVS_CFLOAT_SIZE		0x1000 	/* 4*1024(Byte) = 1024(WORD) = 0x400(Hex) */
//#define FGVS_CINT_SIZE		0x40 	/* 256(Byte) = 64(WORD) = 0x40(Hex) */
//#define FGVS_CBOOL_SIZE		0x1 	/* 4(Byte) = 1(WORD) = 0x1(Hex) */

#define FGVS_INSTMEM_SIZE	0x7FF  /** 8*1024(Byte) = 2048(WORD) = 0x800(Hex) */
#define FGVS_CFLOAT_SIZE	0x3FF  /** 4*1024(Byte) = 1024(WORD) = 0x400(Hex) */
#define FGVS_CINT_SIZE		0xF    /** 256(Byte) = 64(WORD) = 0x40(Hex) */
#define FGVS_CBOOL_SIZE		0x1    /** 4(Byte) = 1(WORD) = 0x1(Hex) */

#define IN_ATTRIB_NUM_MASK			0x000F0000
#define OUT_ATTRIB_NUM_MASK			0x0000000F

/// configuration register
#define PROGRAM_COUNT_COPYOUT		1
/// Related to PC range register
#define PROGRAM_COUNT_END_SHIFT 	16
/// Related to index register of in/output attribute
#define ATTRIBUTE_NUM_SHIFT			16

#define FGSP_ATTRIBUTE_INDEX0		0
#define FGSP_ATTRIBUTE_INDEX1		1
#define FGSP_ATTRIBUTE_INDEX2		2
#define FGSP_ATTRIBUTE_INDEX3		3
#define FGSP_ATTRIBUTE_INDEX4		4
#define FGSP_ATTRIBUTE_INDEX5		5
#define FGSP_ATTRIBUTE_INDEX6		6
#define FGSP_ATTRIBUTE_INDEX7		7
#define FGSP_ATTRIBUTE_INDEX8		8
#define FGSP_ATTRIBUTE_INDEX9		9
#define FGSP_ATTRIBUTE_INDEXA		10
#define FGSP_ATTRIBUTE_INDEXB		11

#define FGSP_MAX_ATTRIBTBL_SIZE		12

#define FGSP_ATTRIB_IO_IDX_MASK     0xF
#define FGSP_ATTRIB_IO_IDX_SHIFT    0x8

/// Pre-defined Attributes for input/output semantic decleration
#define FGSP_ATRBDEF_POSITION 		0x10
#define FGSP_ATRBDEF_NORMAL   		0x20
#define FGSP_ATRBDEF_PCOLOR   		0x40
#define FGSP_ATRBDEF_SCOLOR   		0x41
#define FGSP_ATRBDEF_TEXTURE0 		0x80