📄 sfregrwtest.cpp
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{r_tex3_ctrl, 1, {FGTU_TEX3_CTRL, 0}},
{r_tex3_usize, 1, {FGTU_TEX3_USIZE, 0}},
{r_tex3_vsize, 1, {FGTU_TEX3_VSIZE, 0}},
{r_tex3_psize, 1, {FGTU_TEX3_PSIZE, 0}},
{r_tex3_l1_offset, 1, {FGTU_TEX3_L1_OFFSET, 0}},
{r_tex3_l2_offset, 1, {FGTU_TEX3_L2_OFFSET, 0}},
{r_tex3_l3_offset, 1, {FGTU_TEX3_L3_OFFSET, 0}},
{r_tex3_l4_offset, 1, {FGTU_TEX3_L4_OFFSET, 0}},
{r_tex3_l5_offset, 1, {FGTU_TEX3_L5_OFFSET, 0}},
{r_tex3_l6_offset, 1, {FGTU_TEX3_L6_OFFSET, 0}},
{r_tex3_l7_offset, 1, {FGTU_TEX3_L7_OFFSET, 0}},
{r_tex3_l8_offset, 1, {FGTU_TEX3_L8_OFFSET, 0}},
{r_tex3_l9_offset, 1, {FGTU_TEX3_L9_OFFSET, 0}},
{r_tex3_l10_offset, 1, {FGTU_TEX3_L10_OFFSET, 0}},
{r_tex3_l11_offset, 1, {FGTU_TEX3_L11_OFFSET, 0}},
{r_tex3_min_level, 1, {FGTU_TEX3_MIN_LEVEL, 0}},
{r_tex3_max_level, 1, {FGTU_TEX3_MAX_LEVEL, 0}},
{r_tex3_base_addr, 1, {FGTU_TEX3_BASE_ADDR, 0}},
{r_tex4_ctrl, 1, {FGTU_TEX4_CTRL, 0}},
{r_tex4_usize, 1, {FGTU_TEX4_USIZE, 0}},
{r_tex4_vsize, 1, {FGTU_TEX4_VSIZE, 0}},
{r_tex4_psize, 1, {FGTU_TEX4_PSIZE, 0}},
{r_tex4_l1_offset, 1, {FGTU_TEX4_L1_OFFSET, 0}},
{r_tex4_l2_offset, 1, {FGTU_TEX4_L2_OFFSET, 0}},
{r_tex4_l3_offset, 1, {FGTU_TEX4_L3_OFFSET, 0}},
{r_tex4_l4_offset, 1, {FGTU_TEX4_L4_OFFSET, 0}},
{r_tex4_l5_offset, 1, {FGTU_TEX4_L5_OFFSET, 0}},
{r_tex4_l6_offset, 1, {FGTU_TEX4_L6_OFFSET, 0}},
{r_tex4_l7_offset, 1, {FGTU_TEX4_L7_OFFSET, 0}},
{r_tex4_l8_offset, 1, {FGTU_TEX4_L8_OFFSET, 0}},
{r_tex4_l9_offset, 1, {FGTU_TEX4_L9_OFFSET, 0}},
{r_tex4_l10_offset, 1, {FGTU_TEX4_L10_OFFSET, 0}},
{r_tex4_l11_offset, 1, {FGTU_TEX4_L11_OFFSET, 0}},
{r_tex4_min_level, 1, {FGTU_TEX4_MIN_LEVEL, 0}},
{r_tex4_max_level, 1, {FGTU_TEX4_MAX_LEVEL, 0}},
{r_tex4_base_addr, 1, {FGTU_TEX4_BASE_ADDR, 0}},
{r_tex5_ctrl, 1, {FGTU_TEX5_CTRL, 0}},
{r_tex5_usize, 1, {FGTU_TEX5_USIZE, 0}},
{r_tex5_vsize, 1, {FGTU_TEX5_VSIZE, 0}},
{r_tex5_psize, 1, {FGTU_TEX5_PSIZE, 0}},
{r_tex5_l1_offset, 1, {FGTU_TEX5_L1_OFFSET, 0}},
{r_tex5_l2_offset, 1, {FGTU_TEX5_L2_OFFSET, 0}},
{r_tex5_l3_offset, 1, {FGTU_TEX5_L3_OFFSET, 0}},
{r_tex5_l4_offset, 1, {FGTU_TEX5_L4_OFFSET, 0}},
{r_tex5_l5_offset, 1, {FGTU_TEX5_L5_OFFSET, 0}},
{r_tex5_l6_offset, 1, {FGTU_TEX5_L6_OFFSET, 0}},
{r_tex5_l7_offset, 1, {FGTU_TEX5_L7_OFFSET, 0}},
{r_tex5_l8_offset, 1, {FGTU_TEX5_L8_OFFSET, 0}},
{r_tex5_l9_offset, 1, {FGTU_TEX5_L9_OFFSET, 0}},
{r_tex5_l10_offset, 1, {FGTU_TEX5_L10_OFFSET, 0}},
{r_tex5_l11_offset, 1, {FGTU_TEX5_L11_OFFSET, 0}},
{r_tex5_min_level, 1, {FGTU_TEX5_MIN_LEVEL, 0}},
{r_tex5_max_level, 1, {FGTU_TEX5_MAX_LEVEL, 0}},
{r_tex5_base_addr, 1, {FGTU_TEX5_BASE_ADDR, 0}},
{r_tex6_ctrl, 1, {FGTU_TEX6_CTRL, 0}},
{r_tex6_usize, 1, {FGTU_TEX6_USIZE, 0}},
{r_tex6_vsize, 1, {FGTU_TEX6_VSIZE, 0}},
{r_tex6_psize, 1, {FGTU_TEX6_PSIZE, 0}},
{r_tex6_l1_offset, 1, {FGTU_TEX6_L1_OFFSET, 0}},
{r_tex6_l2_offset, 1, {FGTU_TEX6_L2_OFFSET, 0}},
{r_tex6_l3_offset, 1, {FGTU_TEX6_L3_OFFSET, 0}},
{r_tex6_l4_offset, 1, {FGTU_TEX6_L4_OFFSET, 0}},
{r_tex6_l5_offset, 1, {FGTU_TEX6_L5_OFFSET, 0}},
{r_tex6_l6_offset, 1, {FGTU_TEX6_L6_OFFSET, 0}},
{r_tex6_l7_offset, 1, {FGTU_TEX6_L7_OFFSET, 0}},
{r_tex6_l8_offset, 1, {FGTU_TEX6_L8_OFFSET, 0}},
{r_tex6_l9_offset, 1, {FGTU_TEX6_L9_OFFSET, 0}},
{r_tex6_l10_offset, 1, {FGTU_TEX6_L10_OFFSET, 0}},
{r_tex6_l11_offset, 1, {FGTU_TEX6_L11_OFFSET, 0}},
{r_tex6_min_level, 1, {FGTU_TEX6_MIN_LEVEL, 0}},
{r_tex6_max_level, 1, {FGTU_TEX6_MAX_LEVEL, 0}},
{r_tex6_base_addr, 1, {FGTU_TEX6_BASE_ADDR, 0}},
{r_tex7_ctrl, 1, {FGTU_TEX7_CTRL, 0}},
{r_tex7_usize, 1, {FGTU_TEX7_USIZE, 0}},
{r_tex7_vsize, 1, {FGTU_TEX7_VSIZE, 0}},
{r_tex7_psize, 1, {FGTU_TEX7_PSIZE, 0}},
{r_tex7_l1_offset, 1, {FGTU_TEX7_L1_OFFSET, 0}},
{r_tex7_l2_offset, 1, {FGTU_TEX7_L2_OFFSET, 0}},
{r_tex7_l3_offset, 1, {FGTU_TEX7_L3_OFFSET, 0}},
{r_tex7_l4_offset, 1, {FGTU_TEX7_L4_OFFSET, 0}},
{r_tex7_l5_offset, 1, {FGTU_TEX7_L5_OFFSET, 0}},
{r_tex7_l6_offset, 1, {FGTU_TEX7_L6_OFFSET, 0}},
{r_tex7_l7_offset, 1, {FGTU_TEX7_L7_OFFSET, 0}},
{r_tex7_l8_offset, 1, {FGTU_TEX7_L8_OFFSET, 0}},
{r_tex7_l9_offset, 1, {FGTU_TEX7_L9_OFFSET, 0}},
{r_tex7_l10_offset, 1, {FGTU_TEX7_L10_OFFSET, 0}},
{r_tex7_l11_offset, 1, {FGTU_TEX7_L11_OFFSET, 0}},
{r_tex7_min_level, 1, {FGTU_TEX7_MIN_LEVEL, 0}},
{r_tex7_max_level, 1, {FGTU_TEX7_MAX_LEVEL, 0}},
{r_tex7_base_addr, 1, {FGTU_TEX7_BASE_ADDR, 0}},
{r_color_key1, 1, {FGTU_COLOR_KEY1, 0}},
{r_color_key2, 1, {FGTU_COLOR_KEY2, 0}},
{r_color_key_yuv, 1, {FGTU_COLOR_KEY_YUV, 0}},
{r_color_key_mask, 1, {FGTU_COLOR_KEY_MASK, 0}},
{r_pallete_addr, 1, {FGTU_PALETTE_ADDR, 0}},
{r_pallete_entry, 1, {FGTU_PALETTE_ENTRY, 0}},
{r_vtxtex0_ctrl, 1, {FGTU_VTXTEX0_CTRL, 0}},
{r_vtxtex0_base_addr, 1, {FGTU_VTXTEX0_BASE_ADDR, 0}},
{r_vtxtex1_ctrl, 1, {FGTU_VTXTEX1_CTRL, 0}},
{r_vtxtex1_base_addr, 1, {FGTU_VTXTEX1_BASE_ADDR, 0}},
{r_vtxtex2_ctrl, 1, {FGTU_VTXTEX2_CTRL, 0}},
{r_vtxtex2_base_addr, 1, {FGTU_VTXTEX2_BASE_ADDR, 0}},
{r_vtxtex3_ctrl, 1, {FGTU_VTXTEX3_CTRL, 0}},
{r_vtxtex3_base_addr, 1, {FGTU_VTXTEX3_BASE_ADDR, 0}}
};
default_reg pf_default_regs[] =
{
{r_scissor_xcord, 1, {FGPF_SCISSOR_XCORD, 0}},
{r_scissor_ycord, 1, {FGPF_SCISSOR_YCORD, 0}},
{r_alpha, 1, {FGPF_ALPHA, 0}},
{r_frontface_stencil, 1, {FGPF_FRONTFACE_STENCIL, 0}},
{r_backface_stencil, 1, {FGPF_BACKFACE_STENCIL, 0}},
{r_depth, 1, {FGPF_DEPTH, 0}},
{r_blend_color, 1, {FGPF_BLEND_COLOR, 0}},
{r_blend, 1, {FGPF_BLEND, 0}},
{r_logic_op, 1, {FGPF_LOGIC_OP, 0}},
{r_color_mask, 1, {FGPF_COLOR_MASK, 0}},
{r_depth_mask, 1, {FGPF_STENCIL_DEPTH_MASK,0}},
{r_colorbuf_ctrl, 1, {FGPF_COLORBUF_CTRL, 0}},
{r_depthbuf_addr, 1, {FGPF_DEPTHBUF_ADDR, 0}},
{r_colorbuf_addr, 1, {FGPF_COLORBUF_ADDR, 0}},
{r_colorbuf_width, 1, {FGPF_COLORBUF_WIDTH, 0}}
};
while(1)
{
UART_Printf("\nSFR, Memory Slot Read/Write Test Vector\n");
for (int i=0; (int)rw_menu[i]!=0; i++)
UART_Printf("%2d: %s\n", i, rw_menu[i]);
UART_Printf("\nSelect the function to test : ");
sel = UART_GetIntNum();
UART_Printf("\n");
if(sel == 0)
break;
switch(sel)
{
case 1:
UART_Printf("Global register R/W test start. \n");
ret = sfr_rw_test((pdefault_reg)gb_default_regs, (unsigned int)gb_reg_count);
UART_Printf("Global register R/W test end. \n");
break;
case 2:
UART_Printf("Host Interface register R/W test start. \n");
ret = sfr_rw_test((pdefault_reg)hi_default_regs, (unsigned int)hi_reg_count);
UART_Printf("Host Interface register R/W test end. \n");
break;
case 3:
UART_Printf("Vertex shader contol register R/W test start.\n");
ret = sfr_rw_test((pdefault_reg)vs_default_regs, (unsigned int)vs_reg_count);
UART_Printf("Host Interface register R/W test end. \n");
UART_Printf("Vertex shader memory slots R/W test start.\n");
slot_ret = shader_slot_test((pshader_slot)vs_shader_slots, (unsigned int)r_shader_count);
UART_Printf("Vertex shader memory slots R/W test end.\n");
break;
case 4:
UART_Printf("Primitive engine register R/W test start. \n");
ret = sfr_rw_test((pdefault_reg)pe_default_regs, (unsigned int)pe_reg_count);
UART_Printf("Primitive engine register R/W test end. \n");
break;
case 5:
UART_Printf("Raster engine register R/W test start. \n");
ret = sfr_rw_test((pdefault_reg)ra_default_regs, (unsigned int)ra_reg_count);
UART_Printf("Raster engine register R/W test end. \n");
break;
case 6:
UART_Printf("Pixel shader contol register & memory slots R/W test start.\n");
ret = sfr_rw_test((pdefault_reg)ps_default_regs, (unsigned int)ps_reg_count);
UART_Printf("Pixel shader contol register & memory slots R/W test end.\n");
UART_Printf("Pixel shader memory slots R/W test start.\n");
slot_ret = shader_slot_test((pshader_slot)ps_shader_slots, (unsigned int)r_shader_count);
UART_Printf("Pixel shader memory slots R/W test end.\n");
break;
case 7:
UART_Printf("Texture unit register R/W test start. \n");
ret = sfr_rw_test((pdefault_reg)tu_default_regs, (unsigned int)tu_reg_count);
UART_Printf("Texture unit register R/W test end. \n");
break;
case 8:
UART_Printf("Per-fragment register R/W test start. \n");
ret = sfr_rw_test((pdefault_reg)pf_default_regs, (unsigned int)pf_reg_count);
UART_Printf("Per-fragment register R/W test end. \n");
break;
default:
break;
}
if(ret > 0 )
{
UART_Printf("Total %d error occurred to %s.\n", ret, rw_menu[sel]);
ret = 0;
}
if(slot_ret != NO_ERROR)
{
UART_Printf("Break out, Error occured to 0x%8X in %s.\n", slot_ret, rw_menu[sel]);
}
else
{
UART_Printf("Memory slot r/w test in %s ----------------------- OK.\n", rw_menu[sel]);
}
}
return NO_ERROR;
}
unsigned int sfr_rw_test(pdefault_reg p_default_reg, unsigned int size)
{
unsigned int num_error = 0;
do
{
if(p_default_reg->writable)
{
WRITEREG(p_default_reg->reg.addr, p_default_reg->reg.val);
if(p_default_reg->reg.val != READREG(p_default_reg->reg.addr))
{
UART_Printf(">>>0x%8X ---------------------- FAIL\n", p_default_reg->reg.addr);
num_error++;
}
else {
UART_Printf("0x%8X ---------------------- OK\n", p_default_reg->reg.addr);
}
}
else {
UART_Printf("0x%8X ---------------------- ONLY READ\n", p_default_reg->reg.addr);
}
++p_default_reg;
} while(--size != 0);
return num_error;
}
unsigned int shader_slot_test(pshader_slot p_shader_slot, unsigned int size)
{
unsigned int mem_size;
unsigned int start_addr;
unsigned int comp_value = 0;
unsigned int fault_addr = 0;
do
{
mem_size = p_shader_slot->mem.size;
start_addr = p_shader_slot->mem.start_addr;
switch(p_shader_slot->index)
{
case r_shader_instruction_slot:
case r_shader_const_float_slot:
comp_value = 0xFFFFFFFF;
break;
case r_shader_const_int_slot:
comp_value = 0x00FFFFFF;
break;
case r_shader_const_bool_slot:
comp_value = 0x0000FFFF;
break;
}
do
{
WRITEREG(start_addr, comp_value);
if((start_addr & 0x0000000F) != 0xC )
{
if(comp_value != READREG(start_addr))
{
fault_addr = start_addr;
return fault_addr;
}
}
start_addr += 4;
} while(--mem_size != 0);
++p_shader_slot;
} while(--size != 0);
return NO_ERROR;
}
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