📄 ac11-3.lst
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__text_start:
__start:
0031 E5CF LDI R28,0x5F
0032 E0D4 LDI R29,4
0033 BFCD OUT 0x3D,R28
0034 BFDE OUT 0x3E,R29
0035 51C0 SUBI R28,0x10
0036 40D0 SBCI R29,0
0037 EA0A LDI R16,0xAA
0038 8308 STD Y+0,R16
0039 2400 CLR R0
003A E6E0 LDI R30,0x60
003B E0F0 LDI R31,0
003C E010 LDI R17,0
003D 36ED CPI R30,0x6D
003E 07F1 CPC R31,R17
003F F011 BEQ 0x0042
0040 9201 ST R0,Z+
0041 CFFB RJMP 0x003D
0042 8300 STD Z+0,R16
0043 E6E2 LDI R30,0x62
0044 E0F0 LDI R31,0
0045 E6A0 LDI R26,0x60
0046 E0B0 LDI R27,0
0047 E010 LDI R17,0
0048 36E2 CPI R30,0x62
0049 07F1 CPC R31,R17
004A F021 BEQ 0x004F
004B 95C8 LPM
004C 9631 ADIW R30,1
004D 920D ST R0,X+
004E CFF9 RJMP 0x0048
004F 940E0226 CALL _main
_exit:
0051 CFFF RJMP _exit
FILE: d:\MYDOCU~1\ac11-3\ac11-3.c
(0001) #include <iom16v.h>
(0002) #include<eeprom.h>
(0003) #define uchar unsigned char
(0004) #define uint unsigned int
(0005) uchar const SEG7[10]={0x3f,0x06,0x5b,
(0006) 0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f};
(0007) uchar const ACT[4]={0xfe,0xfd,0xfb,0xf7};
(0008) #define LED1_0 (PORTB=PORTB&0xfe)
(0009) #define S1 (PIND&0x10)
(0010) #define S2 (PIND&0x20)
(0011) #define S3 (PIND&0x40)
(0012) #define S4 (PIND&0x80)
(0013) #define SINT0 (PIND&0x04)
(0014) #define SINT1 (PIND&0x08)
(0015) uchar dpw,dpt,write_flag,time_flag,cnt;
(0016) uint key_cnt,ms_cnt;
(0017) uchar sec,min,set_sec,set_min;
(0018) /************************************************/
(0019) void port_init(void)
(0020) {
(0021) PORTA = 0xFF;
_port_init:
0052 EF8F LDI R24,0xFF
0053 BB8B OUT 0x1B,R24
(0022) DDRA = 0xFF;
0054 BB8A OUT 0x1A,R24
(0023) PORTB = 0xFF;
0055 BB88 OUT 0x18,R24
(0024) DDRB = 0xFF;
0056 BB87 OUT 0x17,R24
(0025) PORTC = 0xFF;
0057 BB85 OUT 0x15,R24
(0026) DDRC = 0xFF;
0058 BB84 OUT 0x14,R24
(0027) PORTD = 0xFF;
0059 BB82 OUT 0x12,R24
(0028) DDRD = 0x00;
005A 2422 CLR R2
005B BA21 OUT 0x11,R2
005C 9508 RET
(0029) }
(0030) //***************************
(0031) void timer0_init(void)
(0032) {
(0033) TCNT0 = 0x83;
_timer0_init:
005D E883 LDI R24,0x83
005E BF82 OUT 0x32,R24
(0034) TCCR0 = 0x03;
005F E083 LDI R24,3
0060 BF83 OUT 0x33,R24
(0035) TIMSK = 0x01;
0061 E081 LDI R24,1
0062 BF89 OUT 0x39,R24
0063 9508 RET
(0036) }
(0037) /*********************************************/
(0038) void init_devices(void)
(0039) {
(0040) port_init();
_init_devices:
0064 DFED RCALL _port_init
(0041) timer0_init();
0065 DFF7 RCALL _timer0_init
(0042) SREG=0x80;
0066 E880 LDI R24,0x80
0067 BF8F OUT 0x3F,R24
0068 9508 RET
_timer0_ovf_isr:
0069 922A ST R2,-Y
006A 923A ST R3,-Y
006B 930A ST R16,-Y
006C 931A ST R17,-Y
006D 932A ST R18,-Y
006E 933A ST R19,-Y
006F 938A ST R24,-Y
0070 939A ST R25,-Y
0071 93EA ST R30,-Y
0072 93FA ST R31,-Y
0073 B62F IN R2,0x3F
0074 922A ST R2,-Y
0075 940E02D5 CALL push_gset1
(0043) }
(0044) //***************************
(0045) #pragma interrupt_handler timer0_ovf_isr:10
(0046) void timer0_ovf_isr(void)
(0047) {
(0048) TCNT0 = 0x83;
0077 E883 LDI R24,0x83
0078 BF82 OUT 0x32,R24
(0049) if(++key_cnt>300)key_cnt=0;
0079 91800066 LDS R24,key_cnt
007B 91900067 LDS R25,key_cnt+1
007D 9601 ADIW R24,1
007E 011C MOVW R2,R24
007F 92300067 STS key_cnt+1,R3
0081 92200066 STS key_cnt,R2
0083 E28C LDI R24,0x2C
0084 E091 LDI R25,1
0085 1582 CP R24,R2
0086 0593 CPC R25,R3
0087 F430 BCC 0x008E
0088 2422 CLR R2
0089 2433 CLR R3
008A 92300067 STS key_cnt+1,R3
008C 92200066 STS key_cnt,R2
(0050) if(++cnt>7)cnt=0;
008E 91800068 LDS R24,cnt
0090 5F8F SUBI R24,0xFF
0091 2E28 MOV R2,R24
0092 92200068 STS cnt,R2
0094 E087 LDI R24,7
0095 1582 CP R24,R2
0096 F418 BCC 0x009A
0097 2422 CLR R2
0098 92200068 STS cnt,R2
(0051) if(++ms_cnt>999){ms_cnt=0;sec++;}
009A 91800064 LDS R24,ms_cnt
009C 91900065 LDS R25,ms_cnt+1
009E 9601 ADIW R24,1
009F 011C MOVW R2,R24
00A0 92300065 STS ms_cnt+1,R3
00A2 92200064 STS ms_cnt,R2
00A4 EE87 LDI R24,0xE7
00A5 E093 LDI R25,3
00A6 1582 CP R24,R2
00A7 0593 CPC R25,R3
00A8 F458 BCC 0x00B4
00A9 2422 CLR R2
00AA 2433 CLR R3
00AB 92300065 STS ms_cnt+1,R3
00AD 92200064 STS ms_cnt,R2
00AF 91800063 LDS R24,sec
00B1 5F8F SUBI R24,0xFF
00B2 93800063 STS sec,R24
(0052) if(sec>59){min++;sec=0;}
00B4 E38B LDI R24,0x3B
00B5 90200063 LDS R2,sec
00B7 1582 CP R24,R2
00B8 F440 BCC 0x00C1
00B9 91800062 LDS R24,min
00BB 5F8F SUBI R24,0xFF
00BC 93800062 STS min,R24
00BE 2422 CLR R2
00BF 92200063 STS sec,R2
(0053) if(min>59)min=59;
00C1 E38B LDI R24,0x3B
00C2 90200062 LDS R2,min
00C4 1582 CP R24,R2
00C5 F410 BCC 0x00C8
00C6 93800062 STS min,R24
(0054) switch(cnt)
00C8 91400068 LDS R20,cnt
00CA 2755 CLR R21
00CB 3040 CPI R20,0
00CC 0745 CPC R20,R21
00CD F121 BEQ 0x00F2
00CE 3041 CPI R20,1
00CF E0E0 LDI R30,0
00D0 075E CPC R21,R30
00D1 F409 BNE 0x00D3
00D2 C032 RJMP 0x0105
00D3 3042 CPI R20,2
00D4 E0E0 LDI R30,0
00D5 075E CPC R21,R30
00D6 F409 BNE 0x00D8
00D7 C040 RJMP 0x0118
00D8 3043 CPI R20,3
00D9 E0E0 LDI R30,0
00DA 075E CPC R21,R30
00DB F409 BNE 0x00DD
00DC C04E RJMP 0x012B
00DD 3044 CPI R20,4
00DE E0E0 LDI R30,0
00DF 075E CPC R21,R30
00E0 F409 BNE 0x00E2
00E1 C05C RJMP 0x013E
00E2 3045 CPI R20,5
00E3 E0E0 LDI R30,0
00E4 075E CPC R21,R30
00E5 F409 BNE 0x00E7
00E6 C07E RJMP 0x0165
00E7 3046 CPI R20,6
00E8 E0E0 LDI R30,0
00E9 075E CPC R21,R30
00EA F409 BNE 0x00EC
00EB C08C RJMP 0x0178
00EC 3047 CPI R20,7
00ED E0E0 LDI R30,0
00EE 075E CPC R21,R30
00EF F409 BNE 0x00F1
00F0 C09A RJMP 0x018B
00F1 C0BF RJMP 0x01B1
(0055) {
(0056) case 0:PORTA=SEG7[sec%10];PORTC=ACT[0];break;
00F2 E02A LDI R18,0xA
00F3 E030 LDI R19,0
00F4 91000063 LDS R16,sec
00F6 2711 CLR R17
00F7 940E028D CALL mod16s
00F9 01F8 MOVW R30,R16
00FA E584 LDI R24,0x54
00FB E090 LDI R25,0
00FC 0FE8 ADD R30,R24
00FD 1FF9 ADC R31,R25
00FE 91E4 LPM R30,0(Z)
00FF BBEB OUT 0x1B,R30
0100 E5EE LDI R30,0x5E
0101 E0F0 LDI R31,0
0102 91E4 LPM R30,0(Z)
0103 BBE5 OUT 0x15,R30
0104 C0AC RJMP 0x01B1
(0057) case 1:PORTA=SEG7[sec/10];PORTC=ACT[1];break;
0105 E02A LDI R18,0xA
0106 E030 LDI R19,0
0107 91000063 LDS R16,sec
0109 2711 CLR R17
010A 940E0291 CALL div16s
010C 01F8 MOVW R30,R16
010D E584 LDI R24,0x54
010E E090 LDI R25,0
010F 0FE8 ADD R30,R24
0110 1FF9 ADC R31,R25
0111 91E4 LPM R30,0(Z)
0112 BBEB OUT 0x1B,R30
0113 E5EF LDI R30,0x5F
0114 E0F0 LDI R31,0
0115 91E4 LPM R30,0(Z)
0116 BBE5 OUT 0x15,R30
0117 C099 RJMP 0x01B1
(0058) case 2:PORTA=SEG7[min%10];PORTC=ACT[2];break;
0118 E02A LDI R18,0xA
0119 E030 LDI R19,0
011A 91000062 LDS R16,min
011C 2711 CLR R17
011D 940E028D CALL mod16s
011F 01F8 MOVW R30,R16
0120 E584 LDI R24,0x54
0121 E090 LDI R25,0
0122 0FE8 ADD R30,R24
0123 1FF9 ADC R31,R25
0124 91E4 LPM R30,0(Z)
0125 BBEB OUT 0x1B,R30
0126 E6E0 LDI R30,0x60
0127 E0F0 LDI R31,0
0128 91E4 LPM R30,0(Z)
0129 BBE5 OUT 0x15,R30
012A C086 RJMP 0x01B1
(0059) case 3:PORTA=SEG7[min/10];PORTC=ACT[3];break;
012B E02A LDI R18,0xA
012C E030 LDI R19,0
012D 91000062 LDS R16,min
012F 2711 CLR R17
0130 940E0291 CALL div16s
0132 01F8 MOVW R30,R16
0133 E584 LDI R24,0x54
0134 E090 LDI R25,0
0135 0FE8 ADD R30,R24
0136 1FF9 ADC R31,R25
0137 91E4 LPM R30,0(Z)
0138 BBEB OUT 0x1B,R30
0139 E6E1 LDI R30,0x61
013A E0F0 LDI R31,0
013B 91E4 LPM R30,0(Z)
013C BBE5 OUT 0x15,R30
013D C073 RJMP 0x01B1
(0060) case 4:if(dpw==1){PORTA=SEG7[set_sec%10]|0x80;}
013E 9180006C LDS R24,dpw
0140 3081 CPI R24,1
0141 F481 BNE 0x0152
0142 E02A LDI R18,0xA
0143 E030 LDI R19,0
0144 91000061 LDS R16,set_sec
0146 2711 CLR R17
0147 940E028D CALL mod16s
0149 01F8 MOVW R30,R16
014A E584 LDI R24,0x54
014B E090 LDI R25,0
014C 0FE8 ADD R30,R24
014D 1FF9 ADC R31,R25
014E 91E4 LPM R30,0(Z)
014F 68E0 ORI R30,0x80
0150 BBEB OUT 0x1B,R30
0151 C00E RJMP 0x0160
(0061) else {PORTA=SEG7[set_sec%10];}
0152 E02A LDI R18,0xA
0153 E030 LDI R19,0
0154 91000061 LDS R16,set_sec
0156 2711 CLR R17
0157 940E028D CALL mod16s
0159 01F8 MOVW R30,R16
015A E584 LDI R24,0x54
015B E090 LDI R25,0
015C 0FE8 ADD R30,R24
015D 1FF9 ADC R31,R25
015E 91E4 LPM R30,0(Z)
015F BBEB OUT 0x1B,R30
(0062) PORTC=ACT[4];break;
0160 E6E2 LDI R30,0x62
0161 E0F0 LDI R31,0
0162 91E4 LPM R30,0(Z)
0163 BBE5 OUT 0x15,R30
0164 C04C RJMP 0x01B1
(0063) case 5:PORTA=SEG7[set_sec/10];PORTC=ACT[5];break;
0165 E02A LDI R18,0xA
0166 E030 LDI R19,0
0167 91000061 LDS R16,set_sec
0169 2711 CLR R17
016A 940E0291 CALL div16s
016C 01F8 MOVW R30,R16
016D E584 LDI R24,0x54
016E E090 LDI R25,0
016F 0FE8 ADD R30,R24
0170 1FF9 ADC R31,R25
0171 91E4 LPM R30,0(Z)
0172 BBEB OUT 0x1B,R30
0173 E6E3 LDI R30,0x63
0174 E0F0 LDI R31,0
0175 91E4 LPM R30,0(Z)
0176 BBE5 OUT 0x15,R30
0177 C039 RJMP 0x01B1
(0064) case 6:PORTA=SEG7[set_min%10];PORTC=ACT[6];break;
0178 E02A LDI R18,0xA
0179 E030 LDI R19,0
017A 91000060 LDS R16,set_min
017C 2711 CLR R17
017D 940E028D CALL mod16s
017F 01F8 MOVW R30,R16
0180 E584 LDI R24,0x54
0181 E090 LDI R25,0
0182 0FE8 ADD R30,R24
0183 1FF9 ADC R31,R25
0184 91E4 LPM R30,0(Z)
0185 BBEB OUT 0x1B,R30
0186 E6E4 LDI R30,0x64
0187 E0F0 LDI R31,0
0188 91E4 LPM R30,0(Z)
0189 BBE5 OUT 0x15,R30
018A C026 RJMP 0x01B1
(0065) case 7:if(dpt==1){PORTA=SEG7[set_min/10]|0x80;}
018B 9180006B LDS R24,dpt
018D 3081 CPI R24,1
018E F481 BNE 0x019F
018F E02A LDI R18,0xA
0190 E030 LDI R19,0
0191 91000060 LDS R16,set_min
0193 2711 CLR R17
0194 940E0291 CALL div16s
0196 01F8 MOVW R30,R16
0197 E584 LDI R24,0x54
0198 E090 LDI R25,0
0199 0FE8 ADD R30,R24
019A 1FF9 ADC R31,R25
019B 91E4 LPM R30,0(Z)
019C 68E0 ORI R30,0x80
019D BBEB OUT 0x1B,R30
019E C00E RJMP 0x01AD
(0066) else {PORTA=SEG7[set_min/10];}
019F E02A LDI R18,0xA
01A0 E030 LDI R19,0
01A1 91000060 LDS R16,set_min
01A3 2711 CLR R17
01A4 940E0291 CALL div16s
01A6 01F8 MOVW R30,R16
01A7 E584 LDI R24,0x54
01A8 E090 LDI R25,0
01A9 0FE8 ADD R30,R24
01AA 1FF9 ADC R31,R25
01AB 91E4 LPM R30,0(Z)
01AC BBEB OUT 0x1B,R30
(0067) PORTC=ACT[7];break;
01AD E6E5 LDI R30,0x65
01AE E0F0 LDI R31,0
01AF 91E4 LPM R30,0(Z)
01B0 BBE5 OUT 0x15,R30
(0068) default:break;
(0069) }
(0070) if(key_cnt==0)
01B1 90200066 LDS R2,key_cnt
01B3 90300067 LDS R3,key_cnt+1
01B5 2022 TST R2
01B6 F009 BEQ 0x01B8
01B7 C049 RJMP 0x0201
01B8 2033 TST R3
01B9 F009 BEQ 0x01BB
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