fs7805reg.h

12864液晶显示

EXTERN xdata volatile BYTE EPBAPLIFTRIG      _AT_ 0xFFE8;  // Endpoint B APLIF Trigger
EXTERN xdata volatile BYTE EPCAPLIFTRIG      _AT_ 0xFFE9;  // Endpoint C APLIF Trigger
EXTERN xdata volatile BYTE EPDAPLIFTRIG      _AT_ 0xFFEA;  // Endpoint D APLIF Trigger
EXTERN xdata volatile BYTE APLIFWAVESEL      _AT_ 0xFFEB;  // Waveform Selector
EXTERN xdata volatile BYTE APLIFS_DAT_H      _AT_ 0xFFEC;  // Read/Write APLIF Data, High Byte
EXTERN xdata volatile BYTE APLIFS_DAT_L      _AT_ 0xFFED;  // Read/Write APLIF Data, Low Byte; No Trigger Transaction
EXTERN xdata volatile BYTE APLIFS_DATX_L     _AT_ 0xFFEE;  // Read/Write APLIF Data, Low Byte, and Trigger Transaction
EXTERN xdata volatile BYTE APLIFTS           _AT_ 0xFFEF;  // APLIF Transaction Status
/*  BYTE Register  */
sfr P0   = 0x80;
sfr P1   = 0x90;
sfr P2   = 0xA0;
sfr P3   = 0xB0;
sfr PSW  = 0xD0;
sfr ACC  = 0xE0;
sfr B    = 0xF0;
sfr SP   = 0x81;
sfr DPL  = 0x82;
sfr DPH  = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0  = 0x8A;
sfr TL1  = 0x8B;
sfr TH0  = 0x8C;
sfr TH1  = 0x8D;
sfr IE   = 0xA8;
sfr IP   = 0xB8;
sfr SCON0 = 0x98;
sfr SBUF0 = 0x99;


/*  BIT Register  */
/*  PSW   */
sbit CY   = 0xD7;
sbit AC   = 0xD6;
sbit F0   = 0xD5;
sbit RS1  = 0xD4;
sbit RS0  = 0xD3;
sbit OV   = 0xD2;
sbit P    = 0xD0;

/*  TCON  */
sbit TF1  = 0x8F;
sbit TR1  = 0x8E;
sbit TF0  = 0x8D;
sbit TR0  = 0x8C;
sbit IE1  = 0x8B;
sbit IT1  = 0x8A;
sbit IE0  = 0x89;
sbit IT0  = 0x88;

/*  IE   */
sbit EA   = 0xAF;
sbit ES   = 0xAC;
sbit ET1  = 0xAB;
sbit EX1  = 0xAA;
sbit ET0  = 0xA9;
sbit EX0  = 0xA8;

/*  IP   */ 
sbit PS   = 0xBC;
sbit PT1  = 0xBB;
sbit PX1  = 0xBA;
sbit PT0  = 0xB9;
sbit PX0  = 0xB8;

/*  P3  */
sbit P3_7   = 0xB7;
sbit P3_6   = 0xB6;
sbit P3_5   = 0xB5;
sbit P3_4   = 0xB4;
sbit P3_3 = 0xB3;
sbit P3_2 = 0xB2;
sbit P3_1  = 0xB1;
sbit P3_0  = 0xB0;

sbit	P2_3 = 0xa3;
sbit	P2_4 = 0xa4;
sbit	P2_5 = 0xa5;

sbit	P0_3 = 0x83;
sbit	P0_0 = 0x80;
sbit	P0_1 = 0x81;

/*  SCON  */
sbit SM0  = 0x9F;
sbit SM1  = 0x9E;
sbit SM2  = 0x9D;
sbit REN  = 0x9C;
sbit TB8  = 0x9B;
sbit RB8  = 0x9A;
sbit TI   = 0x99;
sbit RI   = 0x98;

//-----------------------------------------------------------------------------------------------------------------------------------
//EXTERN xdata volatile BYTE PWM_CTL           _AT_ 0xFE48;  // PWM Control Register
#define bmPWM0_EN		bmBIT0    // PWM0 Enable
#define bmPWM1_EN		bmBIT1    // PWM1 Enable

//EXTERN xdata volatile BYTE CHIPINT         _AT_  0xFE03;  // Chip Interrupt Register
#define bmDMA_INT		bmBIT0    // DMA Interrupt Event Enable
#define bmTDES_INT		bmBIT1    // TDES Interrupt Event Enable
#define bmRNG_INT		bmBIT2    // RNG Interrupt Event Enable
#define bmSPI_INT		bmBIT3    // SPI Interrupt Event Enable
#define bmSDMI_INT		bmBIT4    // SDMI Interrupt Event Enable
#define bmI2C_INT		bmBIT5    // I2C Interrupt Event Enable
#define bmWDT_INT		bmBIT6    // WDT Interrupt Event Enable

//EXTERN xdata volatile BYTE CHIPINTE         _AT_  0xFE04;  // Chip Interrupt Mask Register
#define bmDMA_INT_EN		bmBIT0    // DMA Interrupt Event Enable
#define bmTDES_INT_EN		bmBIT1    // TDES Interrupt Event Enable
#define bmRNG_INT_EN		bmBIT2    // RNG Interrupt Event Enable
#define bmSPI_INT_EN		bmBIT3    // SPI Interrupt Event Enable
#define bmSDMI_INT_EN		bmBIT4    // SDMI Interrupt Event Enable
#define bmI2C_INT_EN		bmBIT5    // I2C Interrupt Event Enable
#define bmWDT_INT_EN		bmBIT6    // WDT Interrupt Event Enable

//EXTERN xdata volatile BYTE SYS_CFG           _AT_ 0xFE05;  // System Configuration Register
#define bmIF_CLK_POL		bmBIT2    // 
#define bmCPU_CLK_OE		bmBIT3    // 
#define bmEX_CLK_EN			bmBIT4    // 
#define bmSYS_SW_RST		bmBIT5    // 
#define bmPM_AVBLE			bmBIT6    // 
#define bmBYPASS_PLL		bmBIT7    // 

//EXTERN xdata volatile BYTE SYSIO_CFG         _AT_ 0xFE06;  // System IO Configuration Register
#define bmSD_EN				bmBIT2    // 
#define bmSPI_EN			bmBIT3    // 
#define bmI2C_EN			bmBIT4    // 
#define bmUART_EN			bmBIT5    // 
#define bmEX_INT_EN			bmBIT6    // 

//EXTERN xdata volatile BYTE DMA_CTL           _AT_ 0xFE40;  // DMA Control
#define bmTDMA_START		bmBIT0    // 
#define bmDMA_START			bmBIT1    // 

//EXTERN xdata volatile BYTE DMA_CTL2          _AT_ 0xFE41;  // DMA Control 2
#define bmCONFLICT_EN		bmBIT0    // 

//EXTERN xdata volatile BYTE TDES_CTL          _AT_ 0xFE78;  // Triple DES Control Register
#define bmTDES_DES_START		bmBIT1    // 
#define bmTDES_DES_SEL			bmBIT2    //
#define bmTDES_DEC_EN			bmBIT3    // 
#define bmTDES_MAC_EN			bmBIT4    // 
#define bmTDES_CLR_DATA			bmBIT5    // 

//SDMI Reg Bit Map------------------------------------------------------------------------
//EXTERN xdata volatile BYTE SDMI_CTL          _AT_ 0xFE31;  // SDMI Control Register
#define bmSD_CLK_EN				bmBIT0    // 
#define bmSD_CLK_SEL			bmBIT1    //
#define bmSD_BUS_4BIT_EN   		bmBIT2    //
#define bmSD_BUS_8BIT_EN   		bmBIT3    //
#define bmSD_AUTO_CLK_EN		bmBIT4    // 

//EXTERN xdata volatile BYTE SDMI_ST          _AT_ 0xFE36;  // SDMI Status Register
#define bmSD_EXIST				bmBIT0    // 
#define bmSD_WR_PROTECT			bmBIT1    //
#define bmSD_BUSY				bmBIT2    //
#define bmSD_CRC16_ERR			bmBIT6    //
#define bmSD_CRC7_ERR			bmBIT7    //
 
//EXTERN xdata volatile BYTE SDMI_INT          _AT_ 0xFE37;  // SDMI Interrupt Register
#define bmSD_COMPLETE_INT		bmBIT0    // 
#define bmSD_STS_CHANGE_INT		bmBIT1    //

//EXTERN xdata volatile BYTE SD_INT_EN         _AT_ 0xFE38;  // SDMI Interrupt Enable Register
#define bmSD_COMPLETE_INT_EN		bmBIT0    // 
#define bmSD_STS_CHANGE_INT_EN		bmBIT1    //
//---------------------------------------------------------------------------------------------

//EXTERN xdata volatile BYTE SW_RST            _AT_ 0xFE13;  // Software Reset Control Register
#define bmUSB_RST				bmBIT0    // 
#define bmSFI_RST				bmBIT1    //
#define bmAPLIF_RST				bmBIT2    //
#define bmSPI_RST				bmBIT3    //
#define bmDMA_RST				bmBIT4    //
#define bmTDES_RST				bmBIT5    //
#define bmSDMI_RST				bmBIT6    //
#define bmI2C_RST				bmBIT7    //


#undef EXTERN
#undef _AT_

#endif