📄 usbdev_+
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HandleEvent_BulkOut();
}
}
// ======================================================================
// endpointZeroFunction()
//
// This is function for Control Transfer.
// If it occurs endpoint0 interrupt, this function is called.
// This function check Device Request for Control Transfer type and
// call each other functions.
// ======================================================================
void USBDEV::HandleEvent_EP0(void)
{
U32 DeviceRequestLength;
U16 ep0csr;
U16 ReadCnt, i;
U16 ReadBuf[64]={0x0000, };
U8 setaddress;
U32 uRemoteWakeUp;
U16 usConfig;
Outp32(INDEX_REG, EP0);
Inp32(EP0_STATUS_REG, ep0csr);
DbgUsb((" Endpoint0 CSR Register = %x \n", ep0csr));
// EP0 CSR register status check
if (ep0csr & EP0_SENT_STALL) // SENT STALL : protocol stall.
{
DbgUsb((" Sent Stall \n"));
Outp32(EP0_STATUS_REG, EP0_SENT_STALL);
if (ep0csr & EP0_RX_SUCCESS)
Outp32(EP0_STATUS_REG, EP0_RX_SUCCESS);
m_uEp0State = EP0_STATE_INIT;
return;
}
if (ep0csr & EP0_TX_SUCCESS)
{
DbgUsb((" EP0_TX_SUCCESS \n"));
Outp32(EP0_STATUS_REG, EP0_TX_SUCCESS);
}
DbgUsb((" m_uEp0State = %x \n", m_uEp0State));
// if ((ep0csr & EP0_RX_SUCCESS) & (m_uEp0State == EP0_STATE_INIT))
if (m_uEp0State == EP0_STATE_INIT)
{
Inp32(BYTE_READ_CNT_REG, ReadCnt);
for(i=0;i<4;i++) Inp32(EP0_FIFO, ReadBuf[i]);
Outp32(EP0_STATUS_REG, EP0_RX_SUCCESS);
m_poDeviceRequest->bmRequestType=ReadBuf[0];
m_poDeviceRequest->bRequest=ReadBuf[0]>>8;
m_poDeviceRequest->wValue_L=ReadBuf[1];
m_poDeviceRequest->wValue_H=ReadBuf[1]>>8;
m_poDeviceRequest->wIndex_L=ReadBuf[2];
m_poDeviceRequest->wIndex_H=ReadBuf[2]>>8;
m_poDeviceRequest->wLength_L=ReadBuf[3];
m_poDeviceRequest->wLength_H=ReadBuf[3]>>8;
PrintEp0Pkt((U8 *)m_poDeviceRequest, 8);
switch (m_poDeviceRequest->bRequest)
{
case STANDARD_SET_ADDRESS:
setaddress = (m_poDeviceRequest->wValue_L); // Set Address Update bit
DbgUsb(("Func_ADDR_Setaddr : %d \n", setaddress));
m_uEp0State = EP0_STATE_INIT;
break;
case STANDARD_SET_DESCRIPTOR:
DbgUsb(("\n MCU >> Set Descriptor \n"));
break;
case STANDARD_SET_CONFIGURATION:
DbgUsb(("\n MCU >> Set Configuration \n"));
usConfig = m_poDeviceRequest->wValue_L; // Configuration value in configuration descriptor
m_uEnumerationDone = 1;
break;
case STANDARD_GET_CONFIGURATION:
// Uart_Printf("\n MCU >> Get Configruation \n");
Outp32(BYTE_WRITE_CNT_REG, 1);
Outp32(EP0_FIFO, usConfig);
break;
case STANDARD_GET_DESCRIPTOR:
switch (m_poDeviceRequest->wValue_H)
{
case DEVICE_DESCRIPTOR:
DbgUsb(("\n MCU >> Get Device Descriptor \n"));
m_uEp0State = EP0_STATE_GD_DEV_0;
break;
case CONFIGURATION_DESCRIPTOR:
DbgUsb(("\n MCU >> Get Configuration Descriptor \n"));
DeviceRequestLength = (U32)((m_poDeviceRequest->wLength_H << 8) |
m_poDeviceRequest->wLength_L);
if (DeviceRequestLength > CONFIG_DESC_SIZE){
// === GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 ===
// Windows98 gets these 4 descriptors all together by issuing only a request.
// Windows2000 gets each descriptor seperately.
// m_uEpZeroTransferLength = CONFIG_DESC_TOTAL_SIZE;
// m_uEpZeroTransferdata = 0;
m_uEp0State = EP0_STATE_GD_CFG_0;
}
else
m_uEp0State = EP0_STATE_GD_CFG_ONLY_0; // for win2k
break;
case STRING_DESCRIPTOR :
switch(m_poDeviceRequest->wValue_L)
{
case 0:
m_uEp0State = EP0_STATE_GD_STR_I0;
break;
case 1:
m_uEp0State = EP0_STATE_GD_STR_I1;
break;
case 2:
m_uEp0State = EP0_STATE_GD_STR_I2;
break;
default:
break;
}
break;
case ENDPOINT_DESCRIPTOR:
switch(m_poDeviceRequest->wValue_L&0xf)
{
case 0:
m_uEp0State=EP0_STATE_GD_EP0_ONLY_0;
break;
case 1:
m_uEp0State=EP0_STATE_GD_EP1_ONLY_0;
break;
default:
break;
}
break;
case DEVICE_QUALIFIER:
DbgUsb(("\n MCU >> Get Device Qualifier Descriptor \n"));
m_uEp0State = EP0_STATE_GD_DEV_QUALIFIER;
break;
}
break;
case STANDARD_CLEAR_FEATURE:
DbgUsb(("\n MCU >> Clear Feature \n"));
switch (m_poDeviceRequest->bmRequestType)
{
case DEVICE_RECIPIENT:
if (m_poDeviceRequest->wValue_L == 1)
uRemoteWakeUp = false;
break;
case ENDPOINT_RECIPIENT:
if (m_poDeviceRequest->wValue_L == 0)
{
if ((m_poDeviceRequest->wIndex_L & 0x7f) == 0x00)
m_poStatusGet->Endpoint0= 0;
if ((m_poDeviceRequest->wIndex_L & 0x8f) == 0x01) // IN Endpoint 1
m_poStatusGet->Endpoint1= 0;
if ((m_poDeviceRequest->wIndex_L & 0x8f) == 0x03) // OUT Endpoint 3
m_poStatusGet->Endpoint3= 0;
}
break;
default:
break;
}
m_uEp0State = EP0_STATE_INIT;
break;
case STANDARD_SET_FEATURE:
DbgUsb(("\n MCU >> Set Feature \n"));
switch (m_poDeviceRequest->bmRequestType)
{
case DEVICE_RECIPIENT:
if (m_poDeviceRequest->wValue_L == 1)
uRemoteWakeUp = true;
break;
case ENDPOINT_RECIPIENT:
if (m_poDeviceRequest->wValue_L == 0)
{
if ((m_poDeviceRequest->wIndex_L & 0x7f) == 0x00)
m_poStatusGet->Endpoint0= 1;
if ((m_poDeviceRequest->wIndex_L & 0x8f) == 0x01)
m_poStatusGet->Endpoint1= 1;
if ((m_poDeviceRequest->wIndex_L & 0x8f) == 0x03)
m_poStatusGet->Endpoint3= 1;
}
break;
default:
break;
}
m_uEp0State = EP0_STATE_INIT;
break;
case STANDARD_GET_STATUS:
switch(m_poDeviceRequest->bmRequestType)
{
case (0x80):
m_poStatusGet->Device=((U8)uRemoteWakeUp<<1)|0x1; // SelfPowered
m_uEp0State = EP0_GET_STATUS0;
break;
case (0x81):
m_poStatusGet->Interface=0;
m_uEp0State = EP0_GET_STATUS1;
break;
case (0x82):
if ((m_poDeviceRequest->wIndex_L & 0x7f) == 0x00)
m_uEp0State = EP0_GET_STATUS2;
if ((m_poDeviceRequest->wIndex_L & 0x8f) == 0x01)
m_uEp0State = EP0_GET_STATUS3;
if ((m_poDeviceRequest->wIndex_L & 0x8f) == 0x03)
m_uEp0State = EP0_GET_STATUS4;
break;
default:
break;
}
break;
case STANDARD_GET_INTERFACE:
m_uEp0State = EP0_INTERFACE_GET;
break;
case STANDARD_SET_INTERFACE:
m_poInterfaceGet->AlternateSetting= m_poDeviceRequest->wValue_L;
m_uEp0State = EP0_STATE_INIT;
break;
case STANDARD_SYNCH_FRAME:
m_uEp0State = EP0_STATE_INIT;
break;
default:
break;
}
}
TransferEp0();
}
// Not Supporting About Set Descriptor for USB Standard
void USBDEV::StandardSetDescriptor(void)
{
// CLR_EP0_CSR_OUT_PACKET_READY;
}
// ======================================================================
// TransferEp0()
//
// This is function for Control Transfer Transmit.
// ======================================================================
void USBDEV::TransferEp0(void)
{
U32 i;
U32 dataLength;
U16 usSysStatus;
// CLR_EP0_CSR_OUT_PACKET_READY;
switch (m_uEp0State)
{
case EP0_STATE_INIT:
break;
// === GET_DESCRIPTOR:DEVICE ===
case EP0_STATE_GD_DEV_0:
if (m_eSpeed == 1)
{
Outp32(BYTE_WRITE_CNT_REG, 18);
WrPktEp0((U8 *)m_poDescDevice+0, 18); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_INIT;
DbgUsb(("EndpointZeroTransfer(EP0_STATE_GD_DEV)\n"));
}
else
{
Outp32(BYTE_WRITE_CNT_REG, 8);
WrPktEp0((U8 *)m_poDescDevice+0, 8); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_GD_DEV_1;
DbgUsb(("EndpointZeroTransfer(EP0_STATE_GD_DEV_0)\n"));
}
break;
case EP0_STATE_GD_DEV_1:
Outp32(BYTE_WRITE_CNT_REG, 8);
WrPktEp0((U8 *)m_poDescDevice+8, 8); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_GD_DEV_2;
DbgUsb(("EndpointZeroTransfer(EP0_STATE_GD_DEV_1)\n"));
break;
case EP0_STATE_GD_DEV_2:
Outp32(BYTE_WRITE_CNT_REG, 2);
WrPktEp0((U8 *)m_poDescDevice+16, 2); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_INIT;
DbgUsb(("EndpointZeroTransfer(EP0_STATE_GD_DEV_2)\n"));
break;
// === GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 ===
// Windows98 gets these 4 descriptors all together by issuing only a request.
// Windows2000 gets each descriptor seperately.
// === GET_DESCRIPTOR:CONFIGURATION ONLY for WIN2K===
case EP0_STATE_GD_CFG_0:
if (m_eSpeed == 1)
{
Outp32(BYTE_WRITE_CNT_REG, 32);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+0, 32); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_INIT;
DbgUsb(("EndpointZeroTransfer(EP0_STATE_GD_CFG)\n"));
}
else
{
Outp32(BYTE_WRITE_CNT_REG, 8);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+0, 8); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_GD_CFG_1;
DbgUsb(("EndpointZeroTransfer(EP0_STATE_GD_CFG_0)\n"));
}
break;
case EP0_STATE_GD_CFG_1:
Outp32(BYTE_WRITE_CNT_REG, 8);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+8, 8); // EP0_PKT_SIZE WrPktEp0((U8 *)&descConf+8, 1); WrPktEp0((U8 *)&descIf+0, 7);
m_uEp0State = EP0_STATE_GD_CFG_2;
break;
case EP0_STATE_GD_CFG_2:
Outp32(BYTE_WRITE_CNT_REG, 8);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+16, 8); // EP0_PKT_SIZE WrPktEp0((U8 *)&descIf+7, 2); WrPktEp0((U8 *)&descEndpt0+0, 6);
m_uEp0State = EP0_STATE_GD_CFG_3;
break;
case EP0_STATE_GD_CFG_3:
Outp32(BYTE_WRITE_CNT_REG, 8);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+24, 8); // EP0_PKT_SIZE WrPktEp0((U8 *)&descEndpt0+6, 1); WrPktEp0((U8 *)&descEndpt1+0, 7);
m_uEp0State = EP0_STATE_GD_CFG_4;
break;
case EP0_STATE_GD_CFG_4:
Outp32(BYTE_WRITE_CNT_REG, 0);
m_uEp0State = EP0_STATE_INIT;
break;
// === GET_DESCRIPTOR:CONFIGURATION ONLY===
case EP0_STATE_GD_CFG_ONLY_0:
if (m_eSpeed == 1)
{
DbgUsb(("[DBG : EP0_STATE_GD_CFG_ONLY]\n"));
Outp32(BYTE_WRITE_CNT_REG, 9);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+0, 9); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_INIT;
}
else
{
DbgUsb(("[DBG : EP0_STATE_GD_CFG_ONLY_0]\n"));
Outp32(BYTE_WRITE_CNT_REG, 8);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+0, 8); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_GD_CFG_ONLY_1;
}
break;
case EP0_STATE_GD_CFG_ONLY_1:
DbgUsb(("[DBG : EP0_STATE_GD_CFG_ONLY_1]\n"));
Outp32(BYTE_WRITE_CNT_REG, 1);
WrPktEp0((U8 *)&m_poDesc->oDescConfig+8, 1); // EP0_PKT_SIZE
m_uEp0State = EP0_STATE_INIT;
break;
// === GET_DESCRIPTOR:INTERFACE ONLY===
case EP0_STATE_GD_IF_ONLY_0:
if (m_eSpeed == 1)
{
Outp32(BYTE_WRITE_CNT_REG, 9); // INTERFACE_DESC_SIZE
WrPktEp0((U8 *)&m_poDesc->oDescInterface+0, 9);
m_uEp0State = EP0_STATE_INIT;
}
else
{
Outp32(BYTE_WRITE_CNT_REG, 8); // INTERFACE_DESC_SIZE
WrPktEp0((U8 *)&m_poDesc->oDescInterface+0, 8);
m_uEp0State = EP0_STATE_GD_IF_ONLY_1;
}
break;
case EP0_STATE_GD_IF_ONLY_1:
Outp32(BYTE_WRITE_CNT_REG, 1);
WrPktEp0((U8 *)&m_poDesc->oDescInterface+8, 1);
m_uEp0State = EP0_STATE_INIT;
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