system.c

Samsung S3C2443 Monitor program source code

#include <stdio.h>
#include "Option.h"
#include "2443addr.h"
#include "System.h"


//===========================[ SYSTEM ]===================================================

//--------------------------------------
//			System clock calculator
//--------------------------------------

static int delayLoopCount;

unsigned int MPLL;
unsigned int ARMCLK, HCLK, PCLK;
unsigned int ARMCLKdiv, PREdiv, HCLKdiv, PCLKdiv;

void SystemCLK(unsigned int prt_msg) // edited by junon 060522, 060624
{
	unsigned int mdiv, pdiv, sdiv;

	mdiv = (rMPLLCON>>16)&0xff;
	pdiv = (rMPLLCON>>8)&0x3;
	sdiv = (rMPLLCON&0x3);

	MPLL = (2*(mdiv+8)*FIN) / (pdiv);
	MPLL >>= sdiv;

	ARMCLKdiv	=	(rCLKDIV0>>9) & 0xf; // [12:9]=ARMDIV -> 1/1 ~ 1/16
	PREdiv      =   (rCLKDIV0>>4) & 0x3;  // [5:4]=PREDIV	   
	HCLKdiv		=	 rCLKDIV0 & 0x3; // [0:1]=HCLKDIV		 
	PCLKdiv		=	(rCLKDIV0>>2) & 1;

	ARMCLK	=	MPLL / ( ((ARMCLKdiv>>3)+1) * ((ARMCLKdiv&7)+1) ); 
	HCLK	=	MPLL / ( ((PREdiv&3)+1) * ((HCLKdiv&3)+1) );
	PCLK	=	HCLK>>PCLKdiv;

	if (prt_msg)
	{
		Console();
		printf("MPLL=%.2fMHz, ARMCLK=%.2fMHz (%d:%d:%d), HCLK=%.2fMHz, PCLK=%.2fMHz\n\n",
   			(float)MPLL/1000000,(float)ARMCLK/1000000,ARMCLKdiv+1,(ARMCLKdiv+1)*(HCLKdiv+1),(ARMCLKdiv+1)*(HCLKdiv+1)*(PCLKdiv+1),(float)HCLK/1000000,(float)PCLK/1000000);
	}
}


//===========================[ Global Library ]===========================================

//--------------------------------------
//			Delay 1 (Watchdog Timer)
//--------------------------------------

void Delay(int time)
{
      // time=0: adjust the Delay function by WatchDog timer.
      // time>0: the number of loop time
      // resolution of time is 100us.
    int i,adjust=0;
    
    if(time==0) 
    {
        time   = 200;
        adjust = 1;
        delayLoopCount = 400;
        //PCLK/1M,Watch-dog disable,1/64,interrupt disable,reset disable
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3); 
        rWTDAT = 0xffff;                              //for first update
        rWTCNT = 0xffff;                              //resolution=64us @any PCLK 
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3)|(1<<5); //Watch-dog timer start
    }
    
    for(;time>0;time--)
        for(i=0;i<delayLoopCount;i++);
    
    if(adjust==1) 
    {
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3);   //Watch-dog timer stop
        i = 0xffff - rWTCNT;                     // 1count->64us, 200*400 cycle runtime = 64*i us
        delayLoopCount = 8000000/(i*64);         //200*400:64*i=1*x:100 -> x=80000*100/(64*i)   
    }
}


//--------------------------------------
//			Delay 2 (Timer 4)
//--------------------------------------

volatile unsigned int TDelayRes = 1000;  // set resolution. [us order : 10us, 100us, 1000us=1ms, 10000us=10ms]
volatile unsigned int TDelayCount = 0;
volatile unsigned int TDelayDone = 0;

void __irq IrqTDelay(void) // Timer 4
{
    TDelayCount--;
    
    if (!TDelayCount)
    {
    	TDelayDone = 1;
		rTCON &= ~(1<<20); // stop timer
    }
    ClearPending(BIT_TIMER4);
}

void SetResTDelay(unsigned int time_res)
{
	TDelayRes = time_res;
}

void InitTDelayFunc(void)  // should be initialized before using TDelay(x)
{
    pISR_TIMER4 = (unsigned )IrqTDelay;
	
    ClearPending(BIT_TIMER4);
	rINTMSK &= ~BIT_TIMER4;

	// make 1MHz Timer clock = PCLK / Prescaler(PCLK/2M-1) + 1 / Divider(2)
	rTCFG0	|=	(PCLK/2000000-1)<<8;		//  prescaler of timer0 [0:7], calc.
	rTCFG1	&=	~(0xf<<16);				//  divider of timer0 [0:3], 1/2 divide
	
	rTCNTB4	=	TDelayRes - 1;		//	make interrupt by "T_RES" us interval.
}

void TDelay(unsigned int d_count)
{
	rINTMSK &= ~BIT_TIMER4;		

	TDelayCount = d_count;
	TDelayDone = 0;
	
	rTCON	|=	(1<<22) | (1<<21);	// auto reload, update data
	rTCON	=	rTCON & ~(1<<21) | (1<<20); // start timer4
	
	while(1)
		if (TDelayDone)	break;

	rINTMSK |= BIT_TIMER4;		
}


//--------------------------------------
//			Stopwatch (Timer 0)
//--------------------------------------

volatile unsigned int TimeRes = 1000;  // set resolution. [us order : 10us, 100us, 1000us=1ms, 10000us=10ms]
volatile unsigned int TimeCount;

void __irq IrqStopwatch(void) // Timer 0
{
    TimeCount++;
    
    ClearPending(BIT_TIMER0);
}

void SetResStopwatch(unsigned int time_res)
{
	TimeRes = time_res;
}

void StartStopwatch(void)
{
    pISR_TIMER0= (unsigned )IrqStopwatch;
	
    ClearPending(BIT_TIMER0);
	rINTMSK &= ~BIT_TIMER0;

	TimeCount = 0;
	
	// make 1MHz Timer clock = PCLK / Prescaler(PCLK/2M-1) + 1 / Divider(2)
	rTCFG0	|=	PCLK/2000000-1;		//  prescaler of timer0 [0:7], calc. for Timer 0,1
	rTCFG1	&=	~(0xf);				//  divider of timer0 [0:3], 1/2 divide
	
	rTCNTB0	=	TimeRes - 1;		//	make interrupt by "T_RES" us interval.
	rTCMPB0	=	0;

	rTCON	|=	(1<<3) | (1<<1);	// auto reload, update data
	rTCON	=	rTCON & ~(1<<1) | (1); // start timer0
}

unsigned int EndStopwatch(void)
{
	unsigned int a;
	
	rTCON = 0; // stop timer
	a = TimeCount * TimeRes + (TimeRes - rTCNTO0);
	rINTMSK |= BIT_TIMER0;
	
	return a;  // unit => us
}


//------------------------------------------------
//	MAX1718 ARM core, internal regulator setting
//------------------------------------------------

void Max1718_Set(int pwr, int voltage)  // add 060624
{

     int vtg;
	//////////////////////////////////////////////
	// GPF3 GPF4 GPF5 GPF6 GPF7
	//  D4   D3   D2   D1   D0
	
	//	0	 0	  0 	0	 0		// 1.75V
	//	0	 0	  0 	0	 1		// 1.70V
	//	0	 0	  0 	1	 0		// 1.65V
	//	0	 0	  0 	1	 1		// 1.60V
	//	0	 0	  1 	0	 0		// 1.55V
	//	0	 0	  1 	0	 1		// 1.50V
	//	0	 0	  1 	1	 0		// 1.45V, Max. voltage of S3C2443 VDDarm
	//	0	 0	  1 	1	 1		// 1.40V
	//	0	 1	  0 	0	 0		// 1.35V
	//	0	 1	  0 	0	 1		// 1.30V
	//	0	 1	  0 	1	 0		// 1.25V
	//	0	 1	  0 	1	 1		// 1.20V
	//	0	 1	  1 	0	 0		// 1.15V
	//	0	 1	  1 	0	 1		// 1.10V
	//	0	 1	  1 	1	 0		// 1.05V
	//	0	 1	  1 	1	 1		// 1.00V
	//	1	 0	  0 	0	 1		// 0.95V
	//	1	 0	  0 	1	 1		// 0.90V
	//	1	 0	  1 	0	 1		// 0.85V
	//	1	 0	  1 	1	 1		// 0.80V
	
    vtg=voltage;
    
    rGPFCON = rGPFCON & ~(0x3ff<<6)|(0x155<<6); // GPF3 ~ 7(Data5 ~ 1): OUTPUT
    rGPFUDP = rGPFUDP & ~(0x3ff<<6)|(0x2aa<<6); // pull down disable
    
    rGPGCON = rGPGCON & ~(0xf<<12)|(0x5<<12); // GPG6(nARM_REG_LE), GPG7(CORE_REG_OE): OUTPUT
    rGPGUDP = rGPGUDP & ~(0xf<<12)|(0xa<<12); // pull down disable
    
    rGPBCON = rGPBCON & ~(0x3<<4)|(0x1<<4); // GPB2(nINT_REG_LE): OUTPUT
    rGPBUDP = rGPBUDP & ~(0x3<<4)|(0x2<<4); // pull down disable


    switch (vtg)
	{
	case 175:
	      rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(0<<5)|(0<<6)|(0<<7);	//D4~0
	      break;

	case 170:
	      rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(0<<5)|(0<<6)|(1<<7);	//D4~0
	      break;

	case 165:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(0<<5)|(1<<6)|(0<<7);	//D4~0
		 break;
       
	case 160:
		rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(0<<5)|(1<<6)|(1<<7);	//D4~0
		break;

	case 155:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(1<<5)|(0<<6)|(0<<7);	//D4~0
		 break;

	case 150:
		rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(1<<5)|(0<<6)|(1<<7);	//D4~0
		 break;

	case 145:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(1<<5)|(1<<6)|(0<<7);	//D4~0
		 break;

	case 140:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(0<<4)|(1<<5)|(1<<6)|(1<<7);	//D4~0
		 break;

	case 135:
	      rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(0<<5)|(0<<6)|(0<<7);	//D4~0
	      break;

	case 130:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(0<<5)|(0<<6)|(1<<7);	//D4~0
		 break;
       
	case 125:
		rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(0<<5)|(1<<6)|(0<<7);	//D4~0
		break;

	case 120:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(0<<5)|(1<<6)|(1<<7);	//D4~0
		 break;

	case 115:
		rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(1<<5)|(0<<6)|(0<<7);	//D4~0
		 break;

	case 110:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(1<<5)|(0<<6)|(1<<7);	//D4~0
		 break;

	case 105:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(1<<5)|(1<<6)|(0<<7);	//D4~0
		 break;

	case 100:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7);	//D4~0
		break;

	case 95:
		rGPFDAT=(rGPFDAT&~(0x1f<<3))|(1<<3)|(0<<4)|(0<<5)|(0<<6)|(1<<7);	//D4~0
		 break;

	case 90:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(1<<3)|(0<<4)|(0<<5)|(1<<6)|(1<<7);	//D4~0
		 break;

	case 85:
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(1<<3)|(0<<4)|(1<<5)|(0<<6)|(1<<7);	//D4~0
		 break;

    case 80:
		rGPFDAT=(rGPFDAT&~(0x1f<<3))|(1<<3)|(0<<4)|(1<<5)|(1<<6)|(1<<7);	//D4~0
		 break;

    default:	// 1.35V
		 rGPFDAT=(rGPFDAT&~(0x1f<<3))|(0<<3)|(1<<4)|(0<<5)|(0<<6)|(0<<7);	//D4~0
		 break;	 		
	}
	
	
	if(pwr)	rGPGDAT&=~(1<<6);   //Arm Latch enable
	else  	rGPBDAT&=~(1<<2);   //Int Latch enable
	
	rGPGDAT|=(1<<7);   //Output enable
	
	if(pwr)	rGPGDAT|=(1<<6);   //Arm Latch disable
	else  	rGPBDAT|=(1<<2);   //Int Latch diaable

}