📄 at91sam9260_inc.h
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// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB Matrix Interface
// *****************************************************************************
// *** Register offset in AT91S_MATRIX structure ***
#define MATRIX_MCFG0 ( 0) // Master Configuration Register 0
#define MATRIX_MCFG1 ( 4) // Master Configuration Register 1
#define MATRIX_MCFG2 ( 8) // Master Configuration Register 2
#define MATRIX_MCFG3 (12) // Master Configuration Register 3
#define MATRIX_MCFG4 (16) // Master Configuration Register 4
#define MATRIX_MCFG5 (20) // Master Configuration Register 5
#define MATRIX_SCFG0 (64) // Slave Configuration Register 0
#define MATRIX_SCFG1 (68) // Slave Configuration Register 1
#define MATRIX_SCFG2 (72) // Slave Configuration Register 2
#define MATRIX_SCFG3 (76) // Slave Configuration Register 3
#define MATRIX_SCFG4 (80) // Slave Configuration Register 4
#define MATRIX_PRAS0 (128) // PRAS0
#define MATRIX_PRAS1 (136) // PRAS1
#define MATRIX_PRAS2 (144) // PRAS2
#define MATRIX_PRAS3 (152) // PRAS3
#define MATRIX_PRAS4 (160) // PRAS4
#define MATRIX_MRCR (256) // Master Remp Control Register
// -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register 0 --------
#define AT91C_MATRIX_ULBT (0x7 << 0) // (MATRIX) Undefined Length Burst Type
// -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register 1 --------
// -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register 2 --------
// -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register 3 --------
// -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register 4 --------
// -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register 5 --------
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ISI (0x3 << 18) // (MATRIX) ISI Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_EMAC (0x4 << 18) // (MATRIX) EMAC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_USB (0x5 << 18) // (MATRIX) USB Master is Default Master
#define AT91C_MATRIX_ARBT (0x3 << 24) // (MATRIX) Arbitration Type
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ISI (0x3 << 18) // (MATRIX) ISI Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_EMAC (0x4 << 18) // (MATRIX) EMAC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_USB (0x5 << 18) // (MATRIX) USB Master is Default Master
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_USB (0x5 << 18) // (MATRIX) USB Master is Default Master
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ISI (0x3 << 18) // (MATRIX) ISI Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_EMAC (0x4 << 18) // (MATRIX) EMAC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_USB (0x5 << 18) // (MATRIX) USB Master is Default Master
// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_USB (0x5 << 18) // (MATRIX) USB Master is Default Master
// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register --------
#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority
#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority
#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority
#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) ISI priority
#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) EMAC priority
#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) USB priority
// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register --------
// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register --------
// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register --------
// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register --------
// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command Bit for ARM926EJ-S Instruction
#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command Bit for ARM926EJ-S Data
#define AT91C_MATRIX_RCB2 (0x1 << 2) // (MATRIX) Remap Command Bit for PDC
#define AT91C_MATRIX_RCB3 (0x1 << 3) // (MATRIX) Remap Command Bit for ISI
#define AT91C_MATRIX_RCB4 (0x1 << 4) // (MATRIX) Remap Command Bit for EMAC
#define AT91C_MATRIX_RCB5 (0x1 << 5) // (MATRIX) Remap Command Bit for USB
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Chip Configuration Registers
// *****************************************************************************
// *** Register offset in AT91S_CCFG structure ***
#define CCFG_EBICSA (12) // EBI Chip Select Assignement Register
#define CCFG_MATRIXVERSION (236) // Version Register
// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register --------
#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
// *** Register offset in AT91S_PDC structure ***
#define PDC_RPR ( 0) // Receive Pointer Register
#define PDC_RCR ( 4) // Receive Counter Register
#define PDC_TPR ( 8) // Transmit Pointer Register
#define PDC_TCR (12) // Transmit Counter Register
#define PDC_RNPR (16) // Receive Next Pointer Register
#define PDC_RNCR (20) // Receive Next Counter Register
#define PDC_TNPR (24) // Transmit Next Pointer Register
#define PDC_TNCR (28) // Transmit Next Counter Register
#define PDC_PTCR (32) // PDC Transfer Control Register
#define PDC_PTSR (36) // PDC Transfer Status Register
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
// *** Register offset in AT91S_DBGU structure ***
#define DBGU_CR ( 0) // Control Register
#define DBGU_MR ( 4) // Mode Register
#define DBGU_IER ( 8) // Interrupt Enable Register
#define DBGU_IDR (12) // Interrupt Disable Register
#define DBGU_IMR (16) // Interrupt Mask Register
#define DBGU_CSR (20) // Channel Status Register
#define DBGU_RHR (24) // Receiver Holding Register
#define DBGU_THR (28) // Transmitter Holding Register
#define DBGU_BRGR (32) // Baud Rate Generator Register
#define DBGU_CIDR (64) // Chip ID Register
#define DBGU_EXID (68) // Chip ID Extension Register
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