ioat91sam9260.ddf

关于at91sam9260的linux全部源代码。

sfr = "DBGU_PTCR.TXTDIS", 	"Memory", 0xfffff320, 4, base=16, bitRange=9
sfr = "DBGU_PTSR", 	"Memory", 0xfffff324, 4, base=16
sfr = "DBGU_PTSR.RXTEN", 	"Memory", 0xfffff324, 4, base=16, bitRange=0
sfr = "DBGU_PTSR.TXTEN", 	"Memory", 0xfffff324, 4, base=16, bitRange=8
; ========== Register definition for DBGU peripheral ========== 
sfr = "DBGU_CR", 	"Memory", 0xfffff200, 4, base=16
sfr = "DBGU_CR.RSTRX", 	"Memory", 0xfffff200, 4, base=16, bitRange=2
sfr = "DBGU_CR.RSTTX", 	"Memory", 0xfffff200, 4, base=16, bitRange=3
sfr = "DBGU_CR.RXEN", 	"Memory", 0xfffff200, 4, base=16, bitRange=4
sfr = "DBGU_CR.RXDIS", 	"Memory", 0xfffff200, 4, base=16, bitRange=5
sfr = "DBGU_CR.TXEN", 	"Memory", 0xfffff200, 4, base=16, bitRange=6
sfr = "DBGU_CR.TXDIS", 	"Memory", 0xfffff200, 4, base=16, bitRange=7
sfr = "DBGU_CR.RSTSTA", 	"Memory", 0xfffff200, 4, base=16, bitRange=8
sfr = "DBGU_MR", 	"Memory", 0xfffff204, 4, base=16
sfr = "DBGU_MR.PAR", 	"Memory", 0xfffff204, 4, base=16, bitRange=9-11
sfr = "DBGU_MR.CHMODE", 	"Memory", 0xfffff204, 4, base=16, bitRange=14-15
sfr = "DBGU_IER", 	"Memory", 0xfffff208, 4, base=16
sfr = "DBGU_IER.RXRDY", 	"Memory", 0xfffff208, 4, base=16, bitRange=0
sfr = "DBGU_IER.TXRDY", 	"Memory", 0xfffff208, 4, base=16, bitRange=1
sfr = "DBGU_IER.ENDRX", 	"Memory", 0xfffff208, 4, base=16, bitRange=3
sfr = "DBGU_IER.ENDTX", 	"Memory", 0xfffff208, 4, base=16, bitRange=4
sfr = "DBGU_IER.OVRE", 	"Memory", 0xfffff208, 4, base=16, bitRange=5
sfr = "DBGU_IER.FRAME", 	"Memory", 0xfffff208, 4, base=16, bitRange=6
sfr = "DBGU_IER.PARE", 	"Memory", 0xfffff208, 4, base=16, bitRange=7
sfr = "DBGU_IER.TXEMPTY", 	"Memory", 0xfffff208, 4, base=16, bitRange=9
sfr = "DBGU_IER.TXBUFE", 	"Memory", 0xfffff208, 4, base=16, bitRange=11
sfr = "DBGU_IER.RXBUFF", 	"Memory", 0xfffff208, 4, base=16, bitRange=12
sfr = "DBGU_IER.TX", 	"Memory", 0xfffff208, 4, base=16, bitRange=30
sfr = "DBGU_IER.RX", 	"Memory", 0xfffff208, 4, base=16, bitRange=31
sfr = "DBGU_IDR", 	"Memory", 0xfffff20c, 4, base=16
sfr = "DBGU_IDR.RXRDY", 	"Memory", 0xfffff20c, 4, base=16, bitRange=0
sfr = "DBGU_IDR.TXRDY", 	"Memory", 0xfffff20c, 4, base=16, bitRange=1
sfr = "DBGU_IDR.ENDRX", 	"Memory", 0xfffff20c, 4, base=16, bitRange=3
sfr = "DBGU_IDR.ENDTX", 	"Memory", 0xfffff20c, 4, base=16, bitRange=4
sfr = "DBGU_IDR.OVRE", 	"Memory", 0xfffff20c, 4, base=16, bitRange=5
sfr = "DBGU_IDR.FRAME", 	"Memory", 0xfffff20c, 4, base=16, bitRange=6
sfr = "DBGU_IDR.PARE", 	"Memory", 0xfffff20c, 4, base=16, bitRange=7
sfr = "DBGU_IDR.TXEMPTY", 	"Memory", 0xfffff20c, 4, base=16, bitRange=9
sfr = "DBGU_IDR.TXBUFE", 	"Memory", 0xfffff20c, 4, base=16, bitRange=11
sfr = "DBGU_IDR.RXBUFF", 	"Memory", 0xfffff20c, 4, base=16, bitRange=12
sfr = "DBGU_IDR.TX", 	"Memory", 0xfffff20c, 4, base=16, bitRange=30
sfr = "DBGU_IDR.RX", 	"Memory", 0xfffff20c, 4, base=16, bitRange=31
sfr = "DBGU_IMR", 	"Memory", 0xfffff210, 4, base=16
sfr = "DBGU_IMR.RXRDY", 	"Memory", 0xfffff210, 4, base=16, bitRange=0
sfr = "DBGU_IMR.TXRDY", 	"Memory", 0xfffff210, 4, base=16, bitRange=1
sfr = "DBGU_IMR.ENDRX", 	"Memory", 0xfffff210, 4, base=16, bitRange=3
sfr = "DBGU_IMR.ENDTX", 	"Memory", 0xfffff210, 4, base=16, bitRange=4
sfr = "DBGU_IMR.OVRE", 	"Memory", 0xfffff210, 4, base=16, bitRange=5
sfr = "DBGU_IMR.FRAME", 	"Memory", 0xfffff210, 4, base=16, bitRange=6
sfr = "DBGU_IMR.PARE", 	"Memory", 0xfffff210, 4, base=16, bitRange=7
sfr = "DBGU_IMR.TXEMPTY", 	"Memory", 0xfffff210, 4, base=16, bitRange=9
sfr = "DBGU_IMR.TXBUFE", 	"Memory", 0xfffff210, 4, base=16, bitRange=11
sfr = "DBGU_IMR.RXBUFF", 	"Memory", 0xfffff210, 4, base=16, bitRange=12
sfr = "DBGU_IMR.TX", 	"Memory", 0xfffff210, 4, base=16, bitRange=30
sfr = "DBGU_IMR.RX", 	"Memory", 0xfffff210, 4, base=16, bitRange=31
sfr = "DBGU_CSR", 	"Memory", 0xfffff214, 4, base=16
sfr = "DBGU_CSR.RXRDY", 	"Memory", 0xfffff214, 4, base=16, bitRange=0
sfr = "DBGU_CSR.TXRDY", 	"Memory", 0xfffff214, 4, base=16, bitRange=1
sfr = "DBGU_CSR.ENDRX", 	"Memory", 0xfffff214, 4, base=16, bitRange=3
sfr = "DBGU_CSR.ENDTX", 	"Memory", 0xfffff214, 4, base=16, bitRange=4
sfr = "DBGU_CSR.OVRE", 	"Memory", 0xfffff214, 4, base=16, bitRange=5
sfr = "DBGU_CSR.FRAME", 	"Memory", 0xfffff214, 4, base=16, bitRange=6
sfr = "DBGU_CSR.PARE", 	"Memory", 0xfffff214, 4, base=16, bitRange=7
sfr = "DBGU_CSR.TXEMPTY", 	"Memory", 0xfffff214, 4, base=16, bitRange=9
sfr = "DBGU_CSR.TXBUFE", 	"Memory", 0xfffff214, 4, base=16, bitRange=11
sfr = "DBGU_CSR.RXBUFF", 	"Memory", 0xfffff214, 4, base=16, bitRange=12
sfr = "DBGU_CSR.TX", 	"Memory", 0xfffff214, 4, base=16, bitRange=30
sfr = "DBGU_CSR.RX", 	"Memory", 0xfffff214, 4, base=16, bitRange=31
sfr = "DBGU_RHR", 	"Memory", 0xfffff218, 4, base=16
sfr = "DBGU_THR", 	"Memory", 0xfffff21c, 4, base=16
sfr = "DBGU_BRGR", 	"Memory", 0xfffff220, 4, base=16
sfr = "DBGU_CIDR", 	"Memory", 0xfffff240, 4, base=16
sfr = "DBGU_EXID", 	"Memory", 0xfffff244, 4, base=16
sfr = "DBGU_FNTR", 	"Memory", 0xfffff248, 4, base=16
sfr = "DBGU_FNTR.NTRST", 	"Memory", 0xfffff248, 4, base=16, bitRange=0
; ========== Register definition for AIC peripheral ========== 
sfr = "AIC_SMR", 	"Memory", 0xfffff000, 4, base=16
sfr = "AIC_SMR.PRIOR", 	"Memory", 0xfffff000, 4, base=16, bitRange=0-2
sfr = "AIC_SMR.SRCTYPE", 	"Memory", 0xfffff000, 4, base=16, bitRange=5-6
sfr = "AIC_SVR", 	"Memory", 0xfffff080, 4, base=16
sfr = "AIC_IVR", 	"Memory", 0xfffff100, 4, base=16
sfr = "AIC_FVR", 	"Memory", 0xfffff104, 4, base=16
sfr = "AIC_ISR", 	"Memory", 0xfffff108, 4, base=16
sfr = "AIC_IPR", 	"Memory", 0xfffff10c, 4, base=16
sfr = "AIC_IMR", 	"Memory", 0xfffff110, 4, base=16
sfr = "AIC_CISR", 	"Memory", 0xfffff114, 4, base=16
sfr = "AIC_CISR.NFIQ", 	"Memory", 0xfffff114, 4, base=16, bitRange=0
sfr = "AIC_CISR.NIRQ", 	"Memory", 0xfffff114, 4, base=16, bitRange=1
sfr = "AIC_IECR", 	"Memory", 0xfffff120, 4, base=16
sfr = "AIC_IDCR", 	"Memory", 0xfffff124, 4, base=16
sfr = "AIC_ICCR", 	"Memory", 0xfffff128, 4, base=16
sfr = "AIC_ISCR", 	"Memory", 0xfffff12c, 4, base=16
sfr = "AIC_EOICR", 	"Memory", 0xfffff130, 4, base=16
sfr = "AIC_SPU", 	"Memory", 0xfffff134, 4, base=16
sfr = "AIC_DCR", 	"Memory", 0xfffff138, 4, base=16
sfr = "AIC_DCR.PROT", 	"Memory", 0xfffff138, 4, base=16, bitRange=0
sfr = "AIC_DCR.GMSK", 	"Memory", 0xfffff138, 4, base=16, bitRange=1
sfr = "AIC_FFER", 	"Memory", 0xfffff140, 4, base=16
sfr = "AIC_FFDR", 	"Memory", 0xfffff144, 4, base=16
sfr = "AIC_FFSR", 	"Memory", 0xfffff148, 4, base=16
; ========== Register definition for PIOA peripheral ========== 
sfr = "PIOA_PER", 	"Memory", 0xfffff400, 4, base=16
sfr = "PIOA_PDR", 	"Memory", 0xfffff404, 4, base=16
sfr = "PIOA_PSR", 	"Memory", 0xfffff408, 4, base=16
sfr = "PIOA_OER", 	"Memory", 0xfffff410, 4, base=16
sfr = "PIOA_ODR", 	"Memory", 0xfffff414, 4, base=16
sfr = "PIOA_OSR", 	"Memory", 0xfffff418, 4, base=16
sfr = "PIOA_IFER", 	"Memory", 0xfffff420, 4, base=16
sfr = "PIOA_IFDR", 	"Memory", 0xfffff424, 4, base=16
sfr = "PIOA_IFSR", 	"Memory", 0xfffff428, 4, base=16
sfr = "PIOA_SODR", 	"Memory", 0xfffff430, 4, base=16
sfr = "PIOA_CODR", 	"Memory", 0xfffff434, 4, base=16
sfr = "PIOA_ODSR", 	"Memory", 0xfffff438, 4, base=16
sfr = "PIOA_PDSR", 	"Memory", 0xfffff43c, 4, base=16
sfr = "PIOA_IER", 	"Memory", 0xfffff440, 4, base=16
sfr = "PIOA_IDR", 	"Memory", 0xfffff444, 4, base=16
sfr = "PIOA_IMR", 	"Memory", 0xfffff448, 4, base=16
sfr = "PIOA_ISR", 	"Memory", 0xfffff44c, 4, base=16
sfr = "PIOA_MDER", 	"Memory", 0xfffff450, 4, base=16
sfr = "PIOA_MDDR", 	"Memory", 0xfffff454, 4, base=16
sfr = "PIOA_MDSR", 	"Memory", 0xfffff458, 4, base=16
sfr = "PIOA_PPUDR", 	"Memory", 0xfffff460, 4, base=16
sfr = "PIOA_PPUER", 	"Memory", 0xfffff464, 4, base=16
sfr = "PIOA_PPUSR", 	"Memory", 0xfffff468, 4, base=16
sfr = "PIOA_ASR", 	"Memory", 0xfffff470, 4, base=16
sfr = "PIOA_BSR", 	"Memory", 0xfffff474, 4, base=16
sfr = "PIOA_ABSR", 	"Memory", 0xfffff478, 4, base=16
sfr = "PIOA_OWER", 	"Memory", 0xfffff4a0, 4, base=16
sfr = "PIOA_OWDR", 	"Memory", 0xfffff4a4, 4, base=16
sfr = "PIOA_OWSR", 	"Memory", 0xfffff4a8, 4, base=16
; ========== Register definition for PIOB peripheral ========== 
sfr = "PIOB_PER", 	"Memory", 0xfffff600, 4, base=16
sfr = "PIOB_PDR", 	"Memory", 0xfffff604, 4, base=16
sfr = "PIOB_PSR", 	"Memory", 0xfffff608, 4, base=16
sfr = "PIOB_OER", 	"Memory", 0xfffff610, 4, base=16
sfr = "PIOB_ODR", 	"Memory", 0xfffff614, 4, base=16
sfr = "PIOB_OSR", 	"Memory", 0xfffff618, 4, base=16
sfr = "PIOB_IFER", 	"Memory", 0xfffff620, 4, base=16
sfr = "PIOB_IFDR", 	"Memory", 0xfffff624, 4, base=16
sfr = "PIOB_IFSR", 	"Memory", 0xfffff628, 4, base=16
sfr = "PIOB_SODR", 	"Memory", 0xfffff630, 4, base=16
sfr = "PIOB_CODR", 	"Memory", 0xfffff634, 4, base=16
sfr = "PIOB_ODSR", 	"Memory", 0xfffff638, 4, base=16
sfr = "PIOB_PDSR", 	"Memory", 0xfffff63c, 4, base=16
sfr = "PIOB_IER", 	"Memory", 0xfffff640, 4, base=16
sfr = "PIOB_IDR", 	"Memory", 0xfffff644, 4, base=16
sfr = "PIOB_IMR", 	"Memory", 0xfffff648, 4, base=16
sfr = "PIOB_ISR", 	"Memory", 0xfffff64c, 4, base=16
sfr = "PIOB_MDER", 	"Memory", 0xfffff650, 4, base=16
sfr = "PIOB_MDDR", 	"Memory", 0xfffff654, 4, base=16
sfr = "PIOB_MDSR", 	"Memory", 0xfffff658, 4, base=16
sfr = "PIOB_PPUDR", 	"Memory", 0xfffff660, 4, base=16
sfr = "PIOB_PPUER", 	"Memory", 0xfffff664, 4, base=16
sfr = "PIOB_PPUSR", 	"Memory", 0xfffff668, 4, base=16
sfr = "PIOB_ASR", 	"Memory", 0xfffff670, 4, base=16
sfr = "PIOB_BSR", 	"Memory", 0xfffff674, 4, base=16
sfr = "PIOB_ABSR", 	"Memory", 0xfffff678, 4, base=16
sfr = "PIOB_OWER", 	"Memory", 0xfffff6a0, 4, base=16
sfr = "PIOB_OWDR", 	"Memory", 0xfffff6a4, 4, base=16
sfr = "PIOB_OWSR", 	"Memory", 0xfffff6a8, 4, base=16
; ========== Register definition for PIOC peripheral ========== 
sfr = "PIOC_PER", 	"Memory", 0xfffff800, 4, base=16
sfr = "PIOC_PDR", 	"Memory", 0xfffff804, 4, base=16
sfr = "PIOC_PSR", 	"Memory", 0xfffff808, 4, base=16
sfr = "PIOC_OER", 	"Memory", 0xfffff810, 4, base=16
sfr = "PIOC_ODR", 	"Memory", 0xfffff814, 4, base=16
sfr = "PIOC_OSR", 	"Memory", 0xfffff818, 4, base=16
sfr = "PIOC_IFER", 	"Memory", 0xfffff820, 4, base=16
sfr = "PIOC_IFDR", 	"Memory", 0xfffff824, 4, base=16
sfr = "PIOC_IFSR", 	"Memory", 0xfffff828, 4, base=16
sfr = "PIOC_SODR", 	"Memory", 0xfffff830, 4, base=16
sfr = "PIOC_CODR", 	"Memory", 0xfffff834, 4, base=16
sfr = "PIOC_ODSR", 	"Memory", 0xfffff838, 4, base=16
sfr = "PIOC_PDSR", 	"Memory", 0xfffff83c, 4, base=16
sfr = "PIOC_IER", 	"Memory", 0xfffff840, 4, base=16
sfr = "PIOC_IDR", 	"Memory", 0xfffff844, 4, base=16
sfr = "PIOC_IMR", 	"Memory", 0xfffff848, 4, base=16
sfr = "PIOC_ISR", 	"Memory", 0xfffff84c, 4, base=16
sfr = "PIOC_MDER", 	"Memory", 0xfffff850, 4, base=16
sfr = "PIOC_MDDR", 	"Memory", 0xfffff854, 4, base=16
sfr = "PIOC_MDSR", 	"Memory", 0xfffff858, 4, base=16
sfr = "PIOC_PPUDR", 	"Memory", 0xfffff860, 4, base=16
sfr = "PIOC_PPUER", 	"Memory", 0xfffff864, 4, base=16
sfr = "PIOC_PPUSR", 	"Memory", 0xfffff868, 4, base=16
sfr = "PIOC_ASR", 	"Memory", 0xfffff870, 4, base=16
sfr = "PIOC_BSR", 	"Memory", 0xfffff874, 4, base=16
sfr = "PIOC_ABSR", 	"Memory", 0xfffff878, 4, base=16
sfr = "PIOC_OWER", 	"Memory", 0xfffff8a0, 4, base=16
sfr = "PIOC_OWDR", 	"Memory", 0xfffff8a4, 4, base=16
sfr = "PIOC_OWSR", 	"Memory", 0xfffff8a8, 4, base=16
; ========== Register definition for CKGR peripheral ========== 
sfr = "CKGR_MOR", 	"Memory", 0xfffffc20, 4, base=16
sfr = "CKGR_MOR.MOSCEN", 	"Memory", 0xfffffc20, 4, base=16, bitRange=0
sfr = "CKGR_MOR.OSCBYPASS", 	"Memory", 0xfffffc20, 4, base=16, bitRange=1
sfr = "CKGR_MOR.OSCOUNT", 	"Memory", 0xfffffc20, 4, base=16, bitRange=8-15
sfr = "CKGR_MCFR", 	"Memory", 0xfffffc24, 4, base=16