init.c

关于测试at91sam9260的各种驱动和功能的测试源代码。

/*************************************** Copyright (c) *************************************************
*
*			            POLAR STAR
*				   北天星国际有限公司
*				   http://www.po-star.com
*
*文 件 名: init.c 
*
*编译环境：ADS1.2
*
********************************************************************************************************/

#include "main.h"


#define AT91C_PLLA_VALUE 	0x2060BF09//0x2014Bf02//0x20483f0e//0x2060BF09 // crystal= 18.432MHz
#define AT91C_SDRAM 		((volatile unsigned int *)0x20000000)

// The following functions must be written in ARM mode this function called directly
// by exception vector
extern void AT91F_Spurious_handler(void);
extern void AT91F_Default_IRQ_handler(void);
extern void AT91F_Default_FIQ_handler(void);
extern void IRQ_Handler_Entry(void);

//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_Printk
//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
//*----------------------------------------------------------------------------
void AT91F_DBGU_Printk(
	char *buffer) // \arg pointer to a string ending by \0
{
	while(*buffer != '\0') {
		while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));
		AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);
	}
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_Wait4KeyPressed
//* \brief 
//*----------------------------------------------------------------------------
unsigned int AT91F_Wait4KeyPressed(void) 
{
    while(!AT91F_US_RxReady((AT91PS_USART)AT91C_BASE_DBGU));
    return((int)AT91F_US_GetChar((AT91PS_USART)AT91C_BASE_DBGU));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DataAbort
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_SpuriousHandler() 
{
	AT91F_DBGU_Printk("-F- Spurious Interrupt detected\n\r");
	while (1);
}


//*----------------------------------------------------------------------------
//* \fn    AT91F_DataAbort
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_DataAbort() 
{
	AT91F_DBGU_Printk("-F- Data Abort detected\n\r");
	while (1);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_FetchAbort
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_FetchAbort()
{
	AT91F_DBGU_Printk("-F- Prefetch Abort detected\n\r");
	while (1);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_Undef
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_Undef() 
{
	AT91F_DBGU_Printk("-F- Undef detected\n\r");
	while (1);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UndefHandler
//* \brief This function reports that no handler have been set for current IT
//*----------------------------------------------------------------------------
void AT91F_UndefHandler() 
{
	AT91F_DBGU_Printk("-F- Undef detected\n\r");
	while (1);
}

//*--------------------------------------------------------------------------------------
//* Function Name       : AT91F_SetPLL
//* Object              : Set the PLLA to 200 and Master clock to 100 Mhz
//* Input Parameters    :
//* Output Parameters   :
//*--------------------------------------------------------------------------------------*/
unsigned int AT91F_SetPLL(void)
{
	AT91PS_PMC pPmc = AT91C_BASE_PMC;
	AT91PS_CKGR pCkgr = AT91C_BASE_CKGR;

	pPmc->PMC_IDR = 0xFFFFFFFF;

	/* -Setup the PLL A */
	pCkgr->CKGR_PLLAR = AT91C_PLLA_VALUE;

	while (!(*AT91C_PMC_SR & AT91C_PMC_LOCKA));
	
	/* - Switch Master Clock from PLLB to PLLA/2 */
	pPmc->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2; 
	while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY));

	return 1;	
}

//*--------------------------------------------------------------------------------------
//* Function Name       : AT91F_InitSdram
//* Object              : Initialize the SDRAM
//* Input Parameters    :
//* Output Parameters   :
//*--------------------------------------------------------------------------------------
void AT91F_InitSDRAM (unsigned int uClock)
{
	volatile unsigned int i;
	AT91PS_SDRAMC	psdrc = AT91C_BASE_SDRAMC;
	
	AT91F_EBI_EnableSDRAMC(AT91C_BASE_CCFG);

	// Configure PIOs
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOC, // PIO controller base address
		((unsigned int) AT91C_PC21_D21     ) |
		((unsigned int) AT91C_PC18_D18     ) |
		((unsigned int) AT91C_PC30_D30     ) |
		((unsigned int) AT91C_PC26_D26     ) |
		((unsigned int) AT91C_PC20_D20     ) |
		((unsigned int) AT91C_PC22_D22     ) |
		((unsigned int) AT91C_PC19_D19     ) |
		((unsigned int) AT91C_PC25_D25     ) |
		((unsigned int) AT91C_PC28_D28     ) |
		((unsigned int) AT91C_PC23_D23     ) |
		((unsigned int) AT91C_PC16_D16     ) |
		((unsigned int) AT91C_PC31_D31     ) |
		((unsigned int) AT91C_PC27_D27     ) |
		((unsigned int) AT91C_PC29_D29     ) |
		((unsigned int) AT91C_PC24_D24     ) |
		((unsigned int) AT91C_PC17_D17     ), // Peripheral A
		0); // Peripheral B
	
	/* CFG 100 */
	if (uClock == AT91C_MASTER_CLOCK)
	{
		psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | 
							AT91C_SDRAMC_NR_13 |
							AT91C_SDRAMC_CAS_2 |
							AT91C_SDRAMC_NB_4_BANKS |
							AT91C_SDRAMC_DBW_32_BITS |
							AT91C_SDRAMC_TWR_2 |
							AT91C_SDRAMC_TRC_7 |
							AT91C_SDRAMC_TRP_2 |
							AT91C_SDRAMC_TRCD_2 |
							AT91C_SDRAMC_TRAS_5 |
							AT91C_SDRAMC_TXSR_8 ;
	}
	else
	{
		psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | 
							AT91C_SDRAMC_NR_13 |
							AT91C_SDRAMC_CAS_2 |
							AT91C_SDRAMC_NB_4_BANKS |
							AT91C_SDRAMC_DBW_32_BITS |
							AT91C_SDRAMC_TWR_1 |
							AT91C_SDRAMC_TRC_4 |
							AT91C_SDRAMC_TRP_1 |
							AT91C_SDRAMC_TRCD_1 |
							AT91C_SDRAMC_TRAS_2 |
							AT91C_SDRAMC_TXSR_3 ;
	}

	for (i =0; i< 1000;i++);

	psdrc->SDRAMC_MR	= 0x00000002;		// Set PRCHG AL
	*AT91C_SDRAM	= 0x00000000;			// Perform PRCHG

	for (i =0; i< 10000;i++);
	
	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
	*(AT91C_SDRAM+4)	= 0x00000001;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 2 CBR
	*(AT91C_SDRAM+8)	= 0x00000002;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 3 CBR
	*(AT91C_SDRAM+0xc)	= 0x00000003;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 4 CBR
	*(AT91C_SDRAM+0x10)	= 0x00000004;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 5 CBR
	*(AT91C_SDRAM+0x14)	= 0x00000005;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 6 CBR
	*(AT91C_SDRAM+0x18)	= 0x00000006;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 7 CBR
	*(AT91C_SDRAM+0x1c)	= 0x00000007;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 8 CBR
	*(AT91C_SDRAM+0x20)	= 0x00000008;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_LMR_CMD;		// Set LMR operation
	*(AT91C_SDRAM+0x24)	= 0xcafedede;						// Perform LMR burst=1, lat=2

	psdrc->SDRAMC_TR	= (uClock * 7)/1000000;	// Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
															// (F : system clock freq. MHz
																														
	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_NORMAL_CMD;		// Set Normal mode
	*AT91C_SDRAM	= 0x00000000;							// Perform Normal mode
}

//*--------------------------------------------------------------------------------------
//* \fn    AT91F_Configure_DBGU
//* \brief 
//*--------------------------------------------------------------------------------------
void AT91F_Configure_DBGU (unsigned int uClock)
{
	// Open PIO for DBGU
	AT91F_DBGU_CfgPIO();
	
	// Configure DBGU
	AT91F_US_Configure(
		(AT91PS_USART)AT91C_BASE_DBGU, // DBGU base address
		uClock,            			   // Master Clock
		AT91C_US_ASYNC_MODE,           // mode Register to be programmed
		115200,                        // baudrate to be programmed
		0                              // timeguard to be programmed
	);

	// Enable Transmitter
	AT91F_US_EnableTx((AT91PS_USART)AT91C_BASE_DBGU);
	// Enable Receiver
	AT91F_US_EnableRx((AT91PS_USART)AT91C_BASE_DBGU);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit(void)
{
	// Disable watchdog
	*(AT91C_WDTC_WDMR) = AT91C_WDTC_WDDIS;

	// Remap	
	if (AT91C_BASE_MATRIX->MATRIX_MRCR != (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D))
		AT91C_BASE_MATRIX->MATRIX_MRCR = (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D);
//	AT91F_MATRIX_Remap_ARM (AT91C_BASE_MATRIX);

/*	if (!AT91F_SetPLL())
		while(1);
*/

// IRQ_Handler_Entry

	// Init Interrupt Controller
	AT91F_AIC_Open(
		AT91C_BASE_AIC,       	 // pointer to the AIC registers
		AT91C_AIC_BRANCH_OPCODE, 	// IRQ exception vector
		AT91F_Default_FIQ_handler,  // \arg Default FIQ vector exception
		AT91F_Default_IRQ_handler, 	// \arg Default Handler set in ISR
		AT91F_Spurious_handler, 	// \arg Default Spurious Handler
		0);        					// Protect mode	AT91C_AIC_DCR_PROT

	// Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ 
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);

	AT91F_AIC_SetExceptionVector((unsigned int *)0x0C, AT91F_FetchAbort);
	AT91F_AIC_SetExceptionVector((unsigned int *)0x10, AT91F_DataAbort);
	AT91F_AIC_SetExceptionVector((unsigned int *)0x4,  AT91F_Undef);
		
 	AT91F_Configure_DBGU (AT91C_MASTER_CLOCK);
}