📄 usb1_ctrl.v
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///////////////////////////////////////////////////////////////////////// //////// Internal Setup Engine //////// //////// //////// Author: Rudolf Usselmann //////// rudi@asics.ws //////// //////// //////// Downloaded from: http://www.opencores.org/cores/usb1_funct///////// ///////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2000-2002 Rudolf Usselmann //////// www.asics.ws //////// rudi@asics.ws //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer.//////// //////// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //////// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //////// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //////// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //////// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //////// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //////// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //////// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //////// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //////// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //////// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //////// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //////// POSSIBILITY OF SUCH DAMAGE. //////// /////////////////////////////////////////////////////////////////////////// CVS Log//// $Id: usb1_ctrl.v,v 1.2 2002/09/25 06:06:49 rudi Exp $//// $Date: 2002/09/25 06:06:49 $// $Revision: 1.2 $// $Author: rudi $// $Locker: $// $State: Exp $//// Change History:// $Log: usb1_ctrl.v,v $// Revision 1.2 2002/09/25 06:06:49 rudi// - Added New Top Level// - Remove old top level and associated files// - Moved FIFOs to "Generic FIFOs" project//// Revision 1.1.1.1 2002/09/19 12:07:09 rudi// Initial Checkin////////////`include "usb1_defines.v"module usb1_ctrl( clk, rst, rom_adr, rom_data, ctrl_setup, ctrl_in, ctrl_out, ep0_din, ep0_dout, ep0_re, ep0_we, ep0_stat, ep0_size, send_stall, frame_no, funct_adr, configured, halt, v_set_int, v_set_feature, wValue, wIndex, vendor_data );input clk, rst;output [6:0] rom_adr;input [7:0] rom_data;//来自rom的数据input ctrl_setup;//来自pl模块input ctrl_in;input ctrl_out;input [7:0] ep0_din;//来自哪个模块？CTRL Endpoint FIFOoutput [7:0] ep0_dout;output ep0_re, ep0_we;input [3:0] ep0_stat;output [7:0] ep0_size;output send_stall;input [10:0] frame_no;//接frm_nat[26:16]output [6:0] funct_adr;output configured, halt;output v_set_int;output v_set_feature;output [15:0] wValue;//他们都给谁了？？output [15:0] wIndex;input [15:0] vendor_data;//16位，用户自定义的数据/////////////////////////////////////////////////////////////////////// Local Wires and Registers//一位热码parameter IDLE = 20'b0000_0000_0000_0000_0001, GET_HDR = 20'b0000_0000_0000_0000_0010,//这个状态也不明！！就是保存主机送来的8字节命令 GET_STATUS_S = 20'b0000_0000_0000_0000_0100, CLEAR_FEATURE_S = 20'b0000_0000_0000_0000_1000, SET_FEATURE_S = 20'b0000_0000_0000_0001_0000, SET_ADDRESS_S = 20'b0000_0000_0000_0010_0000, GET_DESCRIPTOR_S = 20'b0000_0000_0000_0100_0000, SET_DESCRIPTOR_S = 20'b0000_0000_0000_1000_0000, GET_CONFIG_S = 20'b0000_0000_0001_0000_0000, SET_CONFIG_S = 20'b0000_0000_0010_0000_0000, GET_INTERFACE_S = 20'b0000_0000_0100_0000_0000, SET_INTERFACE_S = 20'b0000_0000_1000_0000_0000, SYNCH_FRAME_S = 20'b0000_0001_0000_0000_0000, WAIT_IN_DATA = 20'b0000_0010_0000_0000_0000,//书上反而没有提到,自设的状态 STATUS_IN = 20'b0000_0100_0000_0000_0000,// STATUS_OUT = 20'b0000_1000_0000_0000_0000,// V_SET_INT_S = 20'b0001_0000_0000_0000_0000,//？ V_GET_STATUS_S = 20'b0010_0000_0000_0000_0000;//？wire [7:0] bmReqType, bRequest;//8位wire [15:0] wValue, wIndex, wLength;//16位wire bm_req_dir;//传输方向wire [1:0] bm_req_type;wire [4:0] bm_req_recp;reg get_status, clear_feature, set_feature, set_address;reg get_descriptor, set_descriptor, get_config, set_config;reg get_interface, set_interface, synch_frame;reg hdr_done_r, config_err;//干什么的？reg v_set_int, v_set_feature, v_get_status;//什么含义？wire fifo_re1, fifo_full, fifo_empty;reg fifo_we_d;reg [4:0] data_sel;//5位，用一位热码编码reg ep0_we;//这个是要输出的reg [7:0] ep0_dout;reg [7:0] ep0_size;//这个有什么用？输出的reg send_stall;reg [19:0] state, next_state;//20位reg get_hdr;reg [7:0] le;//读取8字节命令专用wire hdr_done;reg adv;reg [7:0] hdr0, hdr1, hdr2, hdr3, hdr4, hdr5, hdr6, hdr7;//什么？用来存8字节命令reg [6:0] funct_adr;reg set_adr_pending;reg [6:0] funct_adr_tmp;reg in_size_0;reg in_size_1;reg in_size_2;wire high_sel;//这是什么？reg write_done, write_done_r;//干什么的？/////////////////////////////////////////////////////////////////////// FIFO interface//assign ep0_re = fifo_re1;//ep0_re是输出引脚，fifo_re1是wire型assign fifo_empty = ep0_stat[1];//ep0_stat是4位输入assign fifo_full = ep0_stat[2];//fifo_empty,fifo_full是wire型/////////////////////////////////////////////////////////////////////// Current States当前状态//reg addressed;//分配地址了reg configured;//配置了reg halt;//停止wire clr_halt;wire set_halt=0; // FIX_ME，还可以这样赋值啊？？// For this implementation we do not implement HALT for the// device nor for any of the endpoints. This is useless for// this device, but can be added here later ...// FYI, we report device/endpoint errors via interrupts,// instead of halting the entire or part of the device, much// nicer for non-critical errors.assign clr_halt = ctrl_setup;//每次控制传输的setup stage一来就清零always @(posedge clk) if(!rst) addressed <= #1 1'b0; else if(set_address) addressed <= #1 1'b1;//很好理解，表明分配过地址了always @(posedge clk) if(!rst) configured <= #1 1'b0; else if(set_config) configured <= #1 1'b1;//表明配置过了，仅能配置设备always @(posedge clk)//给halt赋值，好象halt永远不会为1了 if(!rst) halt <= #1 1'b0; else if(clr_halt) halt <= #1 1'b0; else if(set_halt) halt <= #1 1'b1;//185行令set_halt=0了/////////////////////////////////////////////////////////////////////// Descriptor ROM，其实是为set_descriptor和get_descriptor作准备的//reg [6:0] rom_adr;//7位reg rom_sel, rom_sel_r;wire rom_done;reg [6:0] rom_size;reg fifo_we_rom_r;//这种信号的含义是什么？reg fifo_we_rom_r2;wire fifo_we_rom;reg [7:0] rom_start_d;reg [6:0] rom_size_dd;wire [6:0] rom_size_d;always @(wValue)//在给rom_start_d赋值，但不知rom_start_d是什么含义，读取rom的起始地址 case(wValue[11:8]) // synopsys full_case parallel_case，wValue共16位，现在正检验高字节的低四位 4'h1: rom_start_d = `ROM_START0;//为一，Device Descriptor Start Address 4'h2: rom_start_d = `ROM_START1;//为二，Configuration Descriptor Start Address 4'h3://为三，字符串描述符的编号，其实这种情况可以暂不考虑，因为在rom中的相关内容被注释掉了 case(wValue[3:0]) // synopsys full_case parallel_casewValue低字节的低四位 4'h00: rom_start_d = `ROM_START2A;//Language ID Descriptor Start Address 4'h01: rom_start_d = `ROM_START2B;//String Descriptor Start Address 4'h02: rom_start_d = `ROM_START2C;//for future use 4'h03: rom_start_d = `ROM_START2D;//for future use default: rom_start_d = `ROM_START2A; endcase default: rom_start_d = 7'h00; endcasealways @(wValue)//在给rom_size_dd赋值，rom_size_dd是七位的reg case(wValue[11:8]) // synopsys full_case parallel_case高字节的值，描述符编号 4'h1: rom_size_dd = `ROM_SIZE0;//Device Descriptor Length 4'h2: rom_size_dd = `ROM_SIZE1;//Configuration Descriptor Length 4'h3: case(wValue[3:0]) // synopsys full_case parallel_case 4'h00: rom_size_dd = `ROM_SIZE2A;//Language ID Descriptor Start Length 4'h01: rom_size_dd = `ROM_SIZE2B;//String Descriptor Length 4'h02: rom_size_dd = `ROM_SIZE2C;//for future use 4'h03: rom_size_dd = `ROM_SIZE2D;//for future use default: rom_size_dd = `ROM_SIZE2A; endcase default: rom_size_dd = 7'h01;//默认长度竟然是1？！ endcaseassign rom_size_d = (rom_size_dd > wLength[6:0]) ? wLength[6:0] : rom_size_dd;//取小的给rom_size_d，看看rom_size_d是否只用于主机接收数据的场合always @(posedge clk)//rom_sel会在后面的状态机里赋值 rom_sel_r <= #1 rom_sel;always @(posedge clk)//给rom_adr赋值，rom_adr为7位 if(!rst) rom_adr <= #1 7'h0; else if(rom_sel & !rom_sel_r) rom_adr <= #1 rom_start_d;//这里的条件表示刚要选通rom的情况，因为rom_sel_r还未觉醒 else if(rom_sel & !fifo_full) rom_adr <= #1 rom_adr + 7'h1;//rom_sel_r已觉醒，但是该写入的数据还没有写完，而且fifo未满always @(posedge clk)//给rom_size赋值，rom_size为7位 if(!rst) rom_size <= #1 7'h0; else if(rom_sel & !rom_sel_r) rom_size <= #1 rom_size_d;//从wLength[6:0] : rom_size_dd中取的小的给rom_size_d else if(rom_sel & !fifo_full) rom_size <= #1 rom_size - 7'h01;//该写入的数据还没有写完always @(posedge clk) fifo_we_rom_r <= #1 rom_sel;//选通rom_sel则可以将rom中的数据写入fifo中？always @(posedge clk) fifo_we_rom_r2 <= #1 fifo_we_rom_r;//一级缓冲assign fifo_we_rom = rom_sel & fifo_we_rom_r2;//这个信号的产生很是严格啊，用的是头级和二级的与信号assign rom_done = (rom_size == 7'h0) & !(rom_sel & !rom_sel_r);//一周目写完，并且没有出现下周目的预兆/////////////////////////////////////////////////////////////////////// Get Header，主要功能是保存来自主机的八字节命令，是setup stage里的data0数据包//assign fifo_re1 = get_hdr & !fifo_empty;//注意ep0_re = fifo_re1，而ep0_re是要输出给接收fifo的always @(posedge clk)//adv是什么？？感觉是将读取时的clk信号二分频 adv <= #1 get_hdr & !fifo_empty & !adv;//变得有点象时钟信号，时高时低always @(posedge clk)//le是8位，一位"1"在左移 if(!rst) le <= #1 8'h0; else if(!get_hdr) le <= #1 8'h0; else if(!(|le)) le <= #1 8'h1;//如果le全零，则le=1 else if(adv) le <= #1 {le[6:0], 1'b0};always @(posedge clk)//给hdrN赋值，hdr为8位。将暂存在接收fifo中的内容保存到ctrl的hdrN寄存器中 if(le[0]) hdr0 <= #1 ep0_din;always @(posedge clk) if(le[1]) hdr1 <= #1 ep0_din;always @(posedge clk) if(le[2]) hdr2 <= #1 ep0_din;always @(posedge clk) if(le[3]) hdr3 <= #1 ep0_din;always @(posedge clk) if(le[4]) hdr4 <= #1 ep0_din;always @(posedge clk) if(le[5]) hdr5 <= #1 ep0_din;always @(posedge clk) if(le[6]) hdr6 <= #1 ep0_din;always @(posedge clk) if(le[7]) hdr7 <= #1 ep0_din;assign hdr_done = le[7] & adv;//8字节存完，hdr_done!感觉是在读取hdr7的同时，hdr_done也置高了/////////////////////////////////////////////////////////////////////// Send Data to Host 返回主机索要的信息//parameter ZERO_DATA = 5'b00001,//又是一位热码 ZERO_ONE_DATA = 5'b00010, CONFIG_DATA = 5'b00100, SYNC_FRAME_DATA = 5'b01000, VEND_DATA = 5'b10000;assign high_sel = write_done_r;//high_sel是选择高字节的意思，write_done_r是不是指低字节传完了，是的，我能肯定了always @(posedge clk)//这里目前还不太明白，这里在设定要传送给主机的数据，返回大小有一字节，有二字节 case(data_sel) // synopsys full_case parallel_case ZERO_DATA: ep0_dout <= #1 rom_sel ? rom_data : 8'h0; ZERO_ONE_DATA: ep0_dout <= #1 high_sel ? 8'h1 : 8'h0;⌨️ 快捷键说明
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