usb1_pl.v

usb1.1 ip核

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Protocol Layer                                             ////
////  This block is typically referred to as the SEI in USB      ////
////  Specification. It encapsulates the Packet Assembler,       ////
////  disassembler, protocol engine and internal DMA             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          [e-mail]                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb1_fucnt/////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         [e-mail]                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: usb1_pl.v,v 1.2 2002/09/25 06:06:49 rudi Exp $
//
//  $Date: 2002/09/25 06:06:49 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: usb1_pl.v,v $
//               Revision 1.2  2002/09/25 06:06:49  rudi
//               - Added New Top Level
//               - Remove old top level and associated files
//               - Moved FIFOs to "Generic FIFOs" project
//
//               Revision 1.1.1.1  2002/09/19 12:07:28  rudi
//               Initial Checkin
//残留问题：idma的理解还有些问题，另外还要对整个pl模块再加强记忆，烂熟于心。
//
//
//
//
//
`include "usb1_defines.v"
//
//

module usb1_pl(	clk, rst,

		// UTMI Interface
		rx_data, rx_valid, rx_active, rx_err,
		tx_data, tx_valid, tx_valid_last, tx_ready,
		tx_first, tx_valid_out,

		token_valid,

		// Register File Interface
		fa,
		ep_sel, 
		x_busy,
		int_crc16_set, int_to_set, int_seqerr_set,

		// Misc
		frm_nat,
		pid_cs_err, nse_err,
		crc5_err,
		rx_size, rx_done,
		ctrl_setup, ctrl_in, ctrl_out,

		// Block Frames
		ep_bf_en, ep_bf_size,
		dropped_frame, misaligned_frame,

		// EP Interface
		csr,
		tx_data_st, rx_data_st, idma_re, idma_we,
		ep_empty, ep_full, send_stall

		);

// UTMI Interface
input		clk, rst;
input	[7:0]	rx_data;
input		rx_valid, rx_active, rx_err;
output	[7:0]	tx_data;
output		tx_valid;
output		tx_valid_last;
input		tx_ready;
output		tx_first;
input		tx_valid_out;//这个在各分立模块中都没有出现,引自utmi接口

output		token_valid;

// Register File interface，与寄存器接口？
input	[6:0]	fa;		// Function Address (as set by the controller)
output	[3:0]	ep_sel;		// Endpoint Number Input
output		x_busy;		// Indicates USB is busy，新家伙

output		int_crc16_set;	// Set CRC16 error interrupt
output		int_to_set;	// Set time out interrupt
output		int_seqerr_set;	// Set PID sequence error interrupt

// Misc
output		pid_cs_err;	// pid checksum error
output		crc5_err;	// crc5 error
output	[31:0]	frm_nat;//32位
output		nse_err;	// no such endpoint error
output	[7:0]	rx_size;//由哪个模块产生？？
output		rx_done;//idma产生
output		ctrl_setup;//由谁产生？
output		ctrl_in;//
output		ctrl_out;//
input		ep_bf_en;//由谁输入？
input	[6:0]	ep_bf_size;//由谁输入？
output		dropped_frame, misaligned_frame;//idma模块产生

// Endpoint Interfaces这个是不是实际的存储器接口？？
input	[13:0]	csr;//这个实际给了pe模块	
input	[7:0]	tx_data_st;//注意它们实际跟谁相连
output	[7:0]	rx_data_st;
output		idma_re, idma_we;//注意它们给谁了
input		ep_empty;//它们从哪里来？
input		ep_full;

input		send_stall;//从何而来？ctrl模块

///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//

// Packet Disassembler Interface
wire		clk, rst;
wire	[7:0]	rx_data;
wire		pid_OUT, pid_IN, pid_SOF, pid_SETUP;
wire		pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
wire		pid_ACK, pid_NACK, pid_STALL, pid_NYET;
wire		pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
wire	[6:0]	token_fadr;//主机分配的设备地址
wire		token_valid;
wire		crc5_err;
wire	[10:0]	frame_no;//pd是要输出11位的frame_no的
reg	[7:0]	rx_data_st;//是pl模块输出脚的reg
wire	[7:0]	rx_data_st_d;//注意是wire型
wire		rx_data_valid;//又是一根电线
wire		rx_data_done;//又是一根电线
wire		crc16_err;//又是一根电线
wire		rx_seq_err;//又是一根电线，这个名字是生的，要注意int_seqerr_set

// Packet Assembler Interface
wire		send_token;
wire	[1:0]	token_pid_sel;
wire		send_data;
wire	[1:0]	data_pid_sel;
wire	[7:0]	tx_data_st;//这根电线干什么的？我觉得根本可以没有这句话
wire	[7:0]	tx_data_st_o;//
wire		rd_next;

// IDMA Interface
wire		rx_dma_en;	// Allows the data to be stored
wire		tx_dma_en;	// Allows for data to be retrieved
wire		abort;		// Abort Transfer (time_out, crc_err or rx_error)注意abort的条件
wire		idma_done;	// DMA is done

// Memory Arbiter Interface
wire		idma_we;//其实他们是用来控制对各个端点fifo
wire		idma_re;

// Local signals
wire		pid_bad;//注意它怎么产生的

reg		hms_clk;	// 0.5 Micro Second Clock，0.5微秒时钟
reg	[4:0]	hms_cnt;//计数器
reg	[10:0]	frame_no_r;	// Current Frame Number register
wire		frame_no_we;//写使能
reg	[11:0]	sof_time;	// Time since last sof，12位
reg		clr_sof_time;
wire		fsel;		// This Function is selected
wire		match_o;//如何产生？

reg		frame_no_we_r;//写使能的寄存器？
reg		ctrl_setup;//可能是用于控制传输的
reg		ctrl_in;
reg		ctrl_out;

wire		idma_we_d;//idma_we的什么关系
wire		ep_empty_int;//用于idma与pa之间的传导