vlx_test_io.v

这是韩国EQUATOR公司提供的DEMO程序

/**
*** Copyright (c) 2001 Equator Technologies, Inc.
**/

//
// vlx_test_io.v
//
// Abstract:
//
// 	Functions as a loopback for GB (e.g., bits fed in are returned back)
//
// Assumptions:
//
//    ~ The vliw thread will write the appropriate DS buffer IDs for i/o into the GB_DATA area.
//    ~ Once started, this thread will idle in a nop loop until the Vlx is turned off.
//    ~ This thread will write a 0 to the semaphore location when complete, to un-stall the vliw thread
//
// Notes :
//    ~ To view the 'status' buffer, on egdb do :
//        (egdb) eti dump pio 0x3a1000 8
//

#include "vas.h"

//
// Define register aliases
//
register gbind_r24     r24;   // GB configuration data
register ramPtr_r14    r14;   // Pointer to vlmem address
register numLoops_r15  r15;   // Number of iterations through loop
register stallAddr_r21 r21;   // Stall location

//
// main()
//
main: {
    nop; // Must have 4 nops at start of main()!!
    nop;
    nop;
    nop;

I_INIT:

    // First, write '0xa1' to vlmem to indicate that the vlx is running
    setacc 0xa1;
    setacc D0_STATUS;
    st lastAcc, acc; 

    // 
    // GB configuration data gets read from memory and written to gb
    // to enable I/O; I/O gets returned back out based on GBDATA settings
    // done outside of this code:  e.g., gbind should contain 2 DS buffer IDs
    // and bit setting to generate I/O out as input stream is shifted; bit 15
    // not set indicates that input read will be echoed out.
    //
    setacc D0_GBDATA;
    ld.w gbind_r24, acc;
    nop;
    gb_dsconf(gbind_r24);
    
    setacc D0_DATA;
    setreg ramPtr_r14;

    //
    // Enable GB input and output, echo output
    //

    // 4 -- if set, enable mpeg DCT processing mode
    // 3 -- specifies what to count for nZero as leading bits : 0 or 1
    // 2 -- if set, count leading bits specified in bit 3, else count type of first bit encountered
    // 1 -- if set, disable input buffer (do not read any more bits into input buffer)
    // 0 -- if set, enable output pre-parse mode (generate output as input is consumed)
    gb_setopt(0b00101); // input enabled, PP mode enabled

    //
    // Decrement where we will start to write since the loop adds one before
    // actual write
    //
    sub.w ramPtr_r14, 1;

    setacc I_GBSTALL;
    setreg stallAddr_r21;

    // Set loop counter

/*
    setacc 32;
    ioif acc, 1; // FBRCNT
    setacc 32;

    setacc 0xa2;
    setacc D0_STATUS;
    st lastAcc, acc; 
*/

    setacc 32;
    setreg numLoops_r15;

    fastloop I_LOOP {
         br stallAddr_r21, if c1_gbstall | c1_acceq0; // check for gb stall
         gb_revsym(16); // OK to shift data through

         //  GB takes 4 cycles to return appropriate symbol value.
         //  It is ok to interleave other operations.  In this case, we interleave
         //  advancing the ramPtr_r14 pointer so we can write to the next location.
         add.w ramPtr_r14, 1;
         nop;
         nop;
         nop;

         //  Write the symbol value received to memory; note that since the GB
         //  does a per byte bit reversal on I/O, these bits will be in a reversed
         //  form from those originally seen at source;  if you want the bits in
         //  the other order, change the gb_getsym(16) above to a gb_revsym(16).
         st symbol, ramPtr_r14;

         //  Decrement the loop counter; note that we decrement this at the end
         //  of the loop so that the acc value is used appropriate in the br.
         sub.w numLoops_r15, 1;
     }

I_SEMA:

    // Clear the semaphore so the vliw code can continue
    setacc 0;        // Data to write
    setacc D1_SEMA;  // Addr to write
    st lastAcc, acc; // Clear semaphore so VLIW will unhalt
    nop;

I_EXIT:

    // First, write '0xaf' to vlmem to indicate we have
    //  reached the exit routine
    setacc 0xaf;
    setacc D0_STATUS+2;
    st lastAcc, acc; 

I_EXIT_2:
    // Always put a 'while(1)' loop at end of vlx program
    nop;
    nop;
    br I_EXIT_2;
    nop;

// 
// GB Stall Routine
//
I_GBSTALL:

    // Check if we exited to to a stall or end-of-loop
    add       numLoops_r15, 0;
    br.acceq0 I_SEMA;

    // Store '0xe1' to vlmem to indicate that we are in stall loop
    setacc 0xe1;
    setacc D0_STATUS+4;
    st lastAcc, acc;  // Store stall code to STATUS
    nop;

I_GBSTALL_2:
    br stallAddr_r21, if c1_gbstall; // if stall continue idle loop
    nop;
    // Store '0xe0' to vlmem to indicate that we have cleared the stall loop
    setacc 0xe0;
    setacc D0_STATUS+4;
    st lastAcc, acc;  
    nop;
    br I_LOOP;  // Return to input shifting loop
    nop;

} // end main()

//
// Lower Data Memory
//
_data0;

D0_STATUS:
data 0x0 (16); // 8 words of 0s (1 word is 16 bits)

D0_DATA @16: // align to 16-word boundary
data 0x0 (64);

D0_GBDATA @16:
data 0x0 (16);

//
// Upper Data Memory
//
_data1;

D1_SEMA @16:
data 0x1234 (4);
data 0x0 (4);