vlc.v

来自「这是韩国EQUATOR公司提供的DEMO程序」· Verilog 代码 · 共 37 行

/**
*** Copyright (c) 2001 Equator Technologies, Inc.
**/

/***************************************
File : vlc.v
***************************************/

  // Set the loop counter
  setacc 16; 
  setreg numLoops_r18;

  setacc D0_DATA;
  setreg ramPtr_r14;

  //
  // I_LOOP
  //   ~ Shift in data, write it to CM1
  //
  I_LOOP:
    call.gbstall pcaddr_r19; // Stall until at least 21 free bits are availble in output buffer
    gb g_hwacc, 0; // 1 => luma, 0 => chroma
    nop;
    nop; 
    nop;
    st symbol, ramPtr_r14;   // CM1[ramPtr_r14] = symbol 
    call.gbstall pcaddr_r19; 
    gb_advance(0);

    add.w ramPtr_r14, 1;   // Increment ptr to CM1
    nop;
    sub.w numLoops_r18, 1; // Decrement loop count
    br.acceq0 I_WRAP_UP;   // If all iterations complete, exit loop
    nop;
    br I_LOOP;             // Else keep looping
    nop;