vfbr.v

这是韩国EQUATOR公司提供的DEMO程序

/**
*** Copyright (c) 2001 Equator Technologies, Inc.
**/

//
// vsema.v
//
// Abstract:
//
// 	Writes some status data to vlmem, then clears semaphore before
//        entering exit loop.
//
// Notes :
//    ~ To view the 'status' buffer, on egdb do :
//        (egdb) eti dump pio 0x3a1010 8
//

#include "vas.h"

register tmpData_r16 r16;
register tmpData_r17 r17;
register tmpAddr_r18 r18;

//
// main()
//
main: {
    nop; // Must have 4 nops at start of main()!!
    nop;
    nop;
    nop;

    setacc 0xa1;
    setacc D0_STATUS+0;
    st lastAcc, acc; 
    nop;
	
    // Set ramoffset just for the heck of it
    setacc 0xf; 
    ioif   acc, 3; // IOIF_RAMOFFSET
    nop;

//----------------------------------------------------------
//
// Test fastbranch
//   ~ First time, test with FBRCNT = infinite
//   ~ First time, test with FBRCNT = infinite
//   ~ Third time, test with FBRCNT = finite, read count
//
//----------------------------------------------------------
I_TEST_FASTBRANCH_FINITE:

#if 1 // This works

    setacc 63;   // finite number of iterations
    ioif acc, 1; // IOIF_FBRCNT

    setacc 0x100;
    setreg tmpData_r17;

#else // This fails

    setacc 0x100;
    setreg tmpData_r17;
    ioif acc, 1; // IOIF_FBRCNT
    setacc 63;   // finite number of iterations
    nop;

#endif

    setacc D0_DATA_FIN;
    setreg tmpAddr_r18;
    nop;

    fastloop MY_FIN {
       st        tmpData_r17, tmpAddr_r18;
       add.w     tmpAddr_r18, 1;
       sub.w     tmpData_r17, 1;
       nop;
       br.acceq0 I_FASTBRANCH_FINITE_END;
    }

I_FASTBRANCH_FINITE_END:
    nop;
    nop;
    nop;
    nop;

//----------------------------------------------------------
// Test fastbranch with count set to run indefinitely
//----------------------------------------------------------
I_TEST_FASTBRANCH_INFINITE:

    setacc 1; // infinite number of iterations
    ioif acc, 1; // IOIF_FBRCNT

    setacc 0x100;
    setreg tmpData_r17;

    setacc D0_DATA_INF;
    setreg tmpAddr_r18;
    nop;

    fastloop MY_FL_INF {
       st        tmpData_r17, tmpAddr_r18;
       add.w     tmpAddr_r18, 1;
       sub.w     tmpData_r17, 1;
       nop;
       br.acceq0 I_FASTBRANCH_INFINITE_END;
    }

I_FASTBRANCH_INFINITE_END:

//----------------------------------------------------------
// Test fastbranch with finite count, read count after exit
//----------------------------------------------------------
I_TEST_FASTBRANCH_READ_COUNT:

  
    setacc 0x2; // Position for hwtaberr
    ioif   acc, 6; // SET
    nop;

    setacc 30; // Actual number of iterations -- result 0x1e in fbrcnt read
               // 0x003a1800 --> 0xffff1e00 0xffff001f 0xffffffff 0xffffffff 
               // 0x003a1810 --> 0xffff3f80 0xffff003f 0xffffffff 0xffffffff 

    //setacc 31; // Actual number of iterations -- result 0x1f in fbrcnt read
               // 0x003a1800 --> 0xffff1f00 0xffff0020 0xffffffff 0xffffffff 
               // 0x003a1810 --> 0xffff3f80 0xffff003f 0xffffffff 0xffffffff 

    setreg tmpData_r16;
    nop;

    setacc 63; // Value to ioif fbrcnt
    setreg tmpData_r17;
    nop;

    setacc 63;   // finite number of iterations
    ioif   acc, 1; // IOIF_FBRCNT
    nop;

    ioif acc, 0; // 0 => READIOIF
    nop;
    st acc, D_DATA + 8 + 0;

    add tmpData_r17, 0; // init 63
    st  acc, D_DATA + 8 + 2;
    nop;

    fastloop MY_COUNT {
       add       tmpData_r16, 0;
       br.acceq0 I_FASTBRANCH_READ_COUNT_END;
       sub.w     tmpData_r16, 1;
       sub.w     tmpData_r17, 1;
       nop;
    }

    nop;
    nop;
    nop;
    nop;

I_FASTBRANCH_READ_COUNT_END:

/*
    READIOIF (0) : reads the values as acc in the following format:
    fbrcnt as bits 15:8
    fastbranch indicator as bit 7
    hwterr as bit 6
    ramoffset value as bits 5:1
*/
   setacc 0xdd; // garbage
   ioif acc, 0; // 0 => READIOIF
   nop;
   st acc, D_DATA + 0;

   add tmpData_r17, 0; // init 63
   st  acc, D_DATA + 2;
   nop;

I_SEMA:

    setacc 0;
    setacc D1_SEMA;
    st lastAcc, acc; // Clear semaphore so vliw will unhalt
    nop;

I_EXIT:

    // Write STATUS buffer
    setacc 0xaf;
    setacc D0_STATUS+2;
    st lastAcc, acc; 
    nop;

I_EXIT_2:

    // Always put a 'while(1)' loop at end of vlx program
    nop;
    br I_EXIT_2;
    nop;

} // end main()

//----------------------------------------------------------------//

//
// Lower Data Memory
//
_data0;

D0_DATA_INF :
data 0x0 (512);

D0_DATA_FIN :
data 0x0 (512);

//
// Upper Data Memory
//
_data1;
D_DATA:
data 0xFFFF (16);

D1_SEMA @16:
data 0x1234 (4);
data 0x0 (12);

D0_STATUS:
data 0x0 (8);