📄 rec.lst
字号:
__text_start:
__start:
16 E5CF LDI R28,0x5F
17 E0D4 LDI R29,4
18 BFCD OUT 0x3D,R28
19 BFDE OUT 0x3E,R29
1A 51C0 SUBI R28,0x10
1B 40D0 SBCI R29,0
1C EA0A LDI R16,0xAA
1D 8308 STD Y+0,R16
1E 2400 CLR R0
1F E6E6 LDI R30,0x66
20 E0F0 LDI R31,0
21 E010 LDI R17,0
22 36EE CPI R30,0x6E
23 07F1 CPC R31,R17
24 F011 BEQ 0x0027
25 9201 ST R0,Z+
26 CFFB RJMP 0x0022
27 8300 STD Z+0,R16
28 E2E6 LDI R30,0x26
29 E0F0 LDI R31,0
2A E6A0 LDI R26,0x60
2B E0B0 LDI R27,0
2C E010 LDI R17,0
2D E000 LDI R16,0
2E BF0B OUT 0x3B,R16
2F 32EC CPI R30,0x2C
30 07F1 CPC R31,R17
31 F021 BEQ 0x0036
32 95C8 LPM
33 9631 ADIW R30,1
34 920D ST R0,X+
35 CFF9 RJMP 0x002F
36 D099 RCALL _main
_exit:
37 CFFF RJMP _exit
FILE: F:\915M\接受\接受.c
(0001) #include <iom8v.h>
(0002) #include <macros.h>
(0003) #include <stdio.h>
(0004) #define DDR_IN 0
(0005) #define DDR_OUT 1
(0006) #define PORT_SEL PORTB
(0007) #define PIN_SEL PINB
(0008) #define DDR_SEL DDRB
(0009)
(0010) #define PORT_SDI PORTB
(0011) #define PIN_SDI PINB
(0012) #define DDR_SDI DDRB
(0013)
(0014) #define PORT_SCK PORTB
(0015) #define PIN_SCK PINB
(0016) #define DDR_SCK DDRB
(0017)
(0018) #define PORT_SDO PORTB
(0019) #define PIN_SDO PINB
(0020) #define DDR_SDO DDRB
(0021)
(0022) #define PB7 7
(0023) #define PB6 6
(0024) #define RFXX_SCK 5
(0025) #define RFXX_SDO 4
(0026) #define RFXX_SDI 3
(0027) #define RFXX_SEL 2
(0028) #define RFXX_DATA 1
(0029) #define PB0 0
(0030)
(0031) #define SEL_OUTPUT() DDR_SEL|=(1<<RFXX_SEL)
(0032) #define HI_SEL() PORT_SEL|=(1<<RFXX_SEL)
(0033) #define LOW_SEL() PORT_SEL&=~(1<<RFXX_SEL)
(0034)
(0035) #define SDI_OUTPUT() DDR_SDI|=(1<<RFXX_SDI)
(0036) #define HI_SDI() PORT_SDI|=(1<<RFXX_SDI)
(0037) #define LOW_SDI() PORT_SDI&=~(1<<RFXX_SDI)
(0038)
(0039) #define SDO_INPUT() DDR_SDO&=~(1<<RFXX_SDO)
(0040) #define SDO_HI() PIN_SDO&=(1<<RFXX_SDO)
(0041) #define SCK_OUTPUT() DDR_SCK|=(1<<RFXX_SCK)
(0042) #define HI_SCK() PORT_SCK|=(1<<RFXX_SCK)
(0043) #define LOW_SCK() PORT_SCK&=~(1<<RFXX_SCK)
(0044)
(0045) #define baud 19200
(0046) #define fosc 8000000
(0047)
(0048) #define uchar unsigned char
(0049) #define uint unsigned int
(0050)
(0051) uchar RF_RXBUF[4];
(0052) uchar ch0,ch1,ch2,ch3; //j,k,l,m;
(0053) uint count1=0,count2=0,speed=50;
(0054)
(0055)
(0056) /*接受芯片端口初始化*/
(0057) void RFXX_PORT_INIT(void)
(0058) {
(0059) HI_SEL();
_RFXX_PORT_INIT:
38 9AC2 SBI 0x18,2
(0060) HI_SDI();
39 9AC3 SBI 0x18,3
(0061) LOW_SCK();
3A 98C5 CBI 0x18,5
(0062) SEL_OUTPUT();
3B 9ABA SBI 0x17,2
(0063) SDI_OUTPUT();
3C 9ABB SBI 0x17,3
(0064) SDO_INPUT();
3D 98BC CBI 0x17,4
(0065) SCK_OUTPUT();
3E 9ABD SBI 0x17,5
3F 9508 RET
_RFXX_WRT_CMD:
temp --> R20
i --> R22
aCmd --> R16
40 D198 RCALL push_xgsetF000
(0066) }
(0067)
(0068) //接受芯片命令写入
(0069) void RFXX_WRT_CMD(uint aCmd)
(0070) {
(0071) uchar i;
(0072) uint temp;
(0073) LOW_SCK();
41 98C5 CBI 0x18,5
(0074) LOW_SEL();
42 98C2 CBI 0x18,2
(0075) for(i=0;i<16;i++)
43 2766 CLR R22
44 C012 RJMP 0x0057
(0076) {
(0077) temp<<=1;
45 0F44 LSL R20
46 1F55 ROL R21
(0078) if(SDO_HI())
47 B386 IN R24,0x16
48 7180 ANDI R24,0x10
49 BB86 OUT 0x16,R24
4A 2388 TST R24
4B F009 BEQ 0x004D
(0079) { temp|=0x0001; }
4C 6041 ORI R20,1
(0080) LOW_SCK();
4D 98C5 CBI 0x18,5
(0081)
(0082) if(aCmd&0x8000) HI_SDI();
4E FF17 SBRS R17,7
4F C002 RJMP 0x0052
50 9AC3 SBI 0x18,3
51 C001 RJMP 0x0053
(0083) else LOW_SDI();
52 98C3 CBI 0x18,3
(0084)
(0085) HI_SCK();
53 9AC5 SBI 0x18,5
(0086) aCmd<<=1;
54 0F00 LSL R16
55 1F11 ROL R17
56 9563 INC R22
57 3160 CPI R22,0x10
58 F360 BCS 0x0045
(0087) }
(0088) LOW_SCK();
59 98C5 CBI 0x18,5
(0089) HI_SEL();
5A 9AC2 SBI 0x18,2
5B C182 RJMP pop_xgsetF000
(0090) // return(temp);
(0091) }
(0092)
(0093) /*接受数据*/
(0094) uchar RF01_RDFIFO(void)
(0095) {
(0096) uchar i,Result;
(0097) LOW_SCK();
_RF01_RDFIFO:
Result --> R16
i --> R18
5C 98C5 CBI 0x18,5
(0098) LOW_SDI();
5D 98C3 CBI 0x18,3
(0099) LOW_SEL();
5E 98C2 CBI 0x18,2
(0100) for(i=0;i<16;i++)
5F 2722 CLR R18
60 C005 RJMP 0x0066
(0101) {
(0102) HI_SCK();
61 9AC5 SBI 0x18,5
(0103) HI_SCK();
62 9AC5 SBI 0x18,5
(0104) LOW_SCK();
63 98C5 CBI 0x18,5
(0105) LOW_SCK();
64 98C5 CBI 0x18,5
65 9523 INC R18
66 3120 CPI R18,0x10
67 F3C8 BCS 0x0061
(0106) }
(0107) Result=0;
68 2700 CLR R16
(0108) for(i=0;i<8;i++)
69 2722 CLR R18
6A C00C RJMP 0x0077
(0109) {
(0110) Result<<=1;
6B 0F00 LSL R16
(0111) if(SDO_HI())
6C B386 IN R24,0x16
6D 7180 ANDI R24,0x10
6E BB86 OUT 0x16,R24
6F 2388 TST R24
70 F009 BEQ 0x0072
(0112) { Result|=1; }
71 6001 ORI R16,1
(0113) HI_SCK();
72 9AC5 SBI 0x18,5
(0114) HI_SCK();
73 9AC5 SBI 0x18,5
(0115) LOW_SCK();
74 98C5 CBI 0x18,5
(0116) LOW_SCK();
75 98C5 CBI 0x18,5
76 9523 INC R18
77 3028 CPI R18,0x8
78 F390 BCS 0x006B
(0117) }
(0118) HI_SEL();
79 9AC2 SBI 0x18,2
(0119) return(Result);
7A 9508 RET
(0120) }
(0121)
(0122) /*字符输出函数*/
(0123) void Transmit(uchar Send_Data)
(0124) {
(0125) while (!(UCSRA & (1<<UDRE)));//判断是否发送完成
_Transmit:
Send_Data --> R16
7B 9B5D SBIS 0x0B,5
7C CFFE RJMP _Transmit
(0126) UDR=Send_Data;//发送数据
7D B90C OUT 0x0C,R16
7E 9508 RET
(0127) }
(0128)
(0129) /*USART初始化*/
(0130) void uart_init(void)
(0131) {
(0132) UCSRA=0x00;
_uart_init:
7F 2422 CLR R2
80 B82B OUT 0x0B,R2
(0133) UCSRB=(1<<RXEN)|(1<<TXEN);//允许发送和接收
81 E188 LDI R24,0x18
82 B98A OUT 0x0A,R24
(0134) UCSRC=(1<<URSEL)|0x06;//8bit,1stop
83 E886 LDI R24,0x86
84 BD80 OUT 0x20,R24
(0135) UBRRL=(fosc/baud/16-1)%256;//设置波特率寄存器低位字节
85 E189 LDI R24,0x19
86 B989 OUT 0x09,R24
(0136) UBRRH=(fosc/baud/16-1)/256;//设置波特率寄存器高位字节
87 BC20 OUT 0x20,R2
88 9508 RET
(0137) }
(0138)
(0139) /*系统初始化*/
(0140) void init_main(void)
(0141) {
(0142) uart_init();
_init_main:
89 DFF5 RCALL _uart_init
(0143) DDRC|=0x30; //PORTC4,PORTC5输出高电平
8A B384 IN R24,0x14
8B 6380 ORI R24,0x30
8C BB84 OUT 0x14,R24
(0144) PORTC|=0x30;
8D B385 IN R24,0x15
8E 6380 ORI R24,0x30
8F BB85 OUT 0x15,R24
(0145) DDRB|=0x03; //PORTB0，PORTB1输出高电平
90 B387 IN R24,0x17
91 6083 ORI R24,3
92 BB87 OUT 0x17,R24
(0146) PORTB|=0x03;
93 B388 IN R24,0x18
94 6083 ORI R24,3
95 BB88 OUT 0x18,R24
(0147) DDRD|=0xE0; //d
96 B381 IN R24,0x11
97 6E80 ORI R24,0xE0
98 BB81 OUT 0x11,R24
(0148) RFXX_PORT_INIT();
99 DF9E RCALL _RFXX_PORT_INIT
(0149)
(0150) RFXX_WRT_CMD(0x0000);
9A 2700 CLR R16
9B 2711 CLR R17
9C DFA3 RCALL _RFXX_WRT_CMD
(0151) RFXX_WRT_CMD(0x998A); //915BAND,134KHZ,998A
9D E80A LDI R16,0x8A
9E E919 LDI R17,0x99
9F DFA0 RCALL _RFXX_WRT_CMD
(0152) RFXX_WRT_CMD(0xA7D0); //915MHZ
A0 ED00 LDI R16,0xD0
A1 EA17 LDI R17,0xA7
A2 DF9D RCALL _RFXX_WRT_CMD
(0153) RFXX_WRT_CMD(0xC847); //4.8kbps,47
A3 E407 LDI R16,0x47
A4 EC18 LDI R17,0xC8
A5 DF9A RCALL _RFXX_WRT_CMD
(0154) RFXX_WRT_CMD(0xC69B); //AFC setting
A6 E90B LDI R16,0x9B
A7 EC16 LDI R17,0xC6
A8 DF97 RCALL _RFXX_WRT_CMD
(0155) RFXX_WRT_CMD(0xC42C); //Clowck recovery manuel control,Digital filter,DQD=4
A9 E20C LDI R16,0x2C
AA EC14 LDI R17,0xC4
AB DF94 RCALL _RFXX_WRT_CMD
(0156) RFXX_WRT_CMD(0xC240); //output 1.66MHz
AC E400 LDI R16,0x40
AD EC12 LDI R17,0xC2
AE DF91 RCALL _RFXX_WRT_CMD
(0157) RFXX_WRT_CMD(0xC080);
AF E800 LDI R16,0x80
B0 EC10 LDI R17,0xC0
B1 DF8E RCALL _RFXX_WRT_CMD
(0158) RFXX_WRT_CMD(0xCE88); //
B2 E808 LDI R16,0x88
B3 EC1E LDI R17,0xCE
B4 DF8B RCALL _RFXX_WRT_CMD
(0159) RFXX_WRT_CMD(0xCE8B); //use FIFO
B5 E80B LDI R16,0x8B
B6 EC1E LDI R17,0xCE
B7 DF88 RCALL _RFXX_WRT_CMD
(0160) RFXX_WRT_CMD(0xC081); //open RX
B8 E801 LDI R16,0x81
B9 EC10 LDI R17,0xC0
BA DF85 RCALL _RFXX_WRT_CMD
(0161)
(0162) DDRB|=(1<<RFXX_DATA);
BB 9AB9 SBI 0x17,1
(0163) DDRD&=~(1<<2);
BC 988A CBI 0x11,2
(0164)
(0165) MCUCR=0x00;
BD 2422 CLR R2
BE BE25 OUT 0x35,R2
(0166) GICR=0x00;
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