emhwlib_propertytypes.h

Sigma SMP8634 Mrua v. 2.8.2.0

/******************************************************/
/* This file is generated automatically, DO NOT EDIT! */
/******************************************************/
/*
 * include/emhwlib_propertytypes.h
 *
 * Copyright (c) 2001-2003 Sigma Designs, Inc. 
 * All Rights Reserved. Proprietary and Confidential.
 *
 */
 
/**
  @file include/emhwlib_propertytypes.h
  @brief emhwlib generated file
   
  @author Jacques Mahe, Christian Wolff, Julien Soulier, Emmanuel Michon
  @ingroup hwlproperties
*/

#ifndef __EMHWLIB_PROPERTYTYPES_H__
#define __EMHWLIB_PROPERTYTYPES_H__

/** struct Default */
struct SystemBlock_GPIO_type {
	/** Member default */
	enum GPIOId_type Bit;
	/** Member default */
	RMbool Data;
};

/** control of the pulse width modulation generators on GPIO pins 14 and 15 */
struct SystemBlock_PWM_type {
	/** PWM generator number. @note 0 for GPIO 14, 1 for GPIO 15 range 0 -> 1 */
	RMuint32 GeneratorNumber;
	/** if TRUE, enables PWM generator on GPIO 14 or 15, overrides GPIO setting */
	RMbool Enable;
	/** Width of the high pulse, translates into a voltage level after a low pass filter range 0 -> 65535 */
	RMuint32 Level;
	/** system clock pre divider. @note The minimum pulse width is equal to 2 ^ (Log2Div + 1) system clock periods. range 0 -> 7 */
	RMuint32 Log2Div;
};

/** struct Default */
struct SystemBlock_DRAMConfig_type {
	/** Member default range 0 -> 2 */
	RMuint32 Controller;
	/** Member default range 0 -> 31 */
	RMuint32 refresh;
	/** Member default range 0 -> 7 */
	RMuint32 tRFC;
	/** Member default range 0 -> 7 */
	RMuint32 CCL;
	/** Member default range 0 -> 7 */
	RMuint32 DCL;
	/** Member default */
	RMbool d;
	/** Member default range 1 -> 3 */
	RMuint32 col;
	/** Member default */
	RMbool a;
	/** Member default */
	RMbool s;
};

/** struct Default */
struct SystemBlock_DRAMDelay_type {
	/** Member default range 0 -> 2 */
	RMuint32 Controller;
	/** Member default range 0 -> 15 */
	RMuint32 DQS0;
	/** Member default range 0 -> 15 */
	RMuint32 DQS1;
	/** Member default range 0 -> 15 */
	RMuint32 DQS2;
	/** Member default range 0 -> 15 */
	RMuint32 DQS3;
	/** Member default range 0 -> 15 */
	RMuint32 Dout;
};

/** struct Default */
struct SystemBlock_DRAMDelayAuto_type {
	/** Member default range 0 -> 2 */
	RMuint32 Controller;
	/** Member default range 0 -> 15 */
	RMuint32 DQS00;
	/** Member default range 0 -> 15 */
	RMuint32 DQS10;
	/** Member default range 0 -> 15 */
	RMuint32 DQS20;
	/** Member default range 0 -> 15 */
	RMuint32 DQS30;
	/** Member default range 0 -> 15 */
	RMuint32 Dout0;
	/** Member default range 0 -> 15 */
	RMuint32 DQS01;
	/** Member default range 0 -> 15 */
	RMuint32 DQS11;
	/** Member default range 0 -> 15 */
	RMuint32 DQS21;
	/** Member default range 0 -> 15 */
	RMuint32 DQS31;
	/** Member default range 0 -> 15 */
	RMuint32 Dout1;
	/** Member default range 0 -> 31 */
	RMuint32 RefMan;
	/** Member default */
	RMbool A;
	/** Member default range 0 -> 31 */
	RMuint32 RefAuto;
	/** Member default range 0 -> 15 */
	RMuint32 min;
	/** Member default range 0 -> 15 */
	RMuint32 range;
};

/** struct Default */
struct SystemBlock_BWMonitorSelection_type {
	/** Member default range 0 -> 1 */
	RMuint32 DRAMControllerId;
	/** Member default */
	RMuint8 ChannelA;
	/** Member default */
	RMuint8 ChannelB;
	/** Member default */
	RMuint8 ChannelC;
	/** Member default */
	RMuint8 ChannelD;
	/** Member default */
	RMuint32 AddressHi;
	/** Member default */
	RMuint32 AddressLo;
	/** Member default */
	RMuint8 ConfigId;
};

/** struct Default */
struct SystemBlock_BWMonitorEnable_type {
	/** Member default range 0 -> 1 */
	RMuint32 DRAMControllerId;
	/** Member default */
	RMbool Enable;
};

/** enum Default */
enum CPUBlock_State_type {
	/** In Enum default */
	CPUBlock_State_RUNNING = 0,
	/** In Enum default */
	CPUBlock_State_STOPPED = 1,
	/** In Enum default */
	CPUBlock_State_RESET = 2,
};

/** struct Default */
struct CPUBlock_ProcessInterrupt_type {
	/** Member default */
	RMuint32 status;
	/** Member default */
	void * context;
};

/** struct Default */
struct CPUBlock_AddDataFifoXferTask_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 priority;
	/** Member default */
	RMuint32 host_notification_threshold;
	/** Member default */
	enum TransferTaskCallback callback;
	/** Member default */
	void * context;
	/** Member default */
	RMuint32 data_fifo;
	/** Member default */
	RMuint32 data_mutex;
	/** Member default */
	RMuint32 pts_fifo;
	/** Member default */
	RMuint32 dmem_base;
	/** Member default */
	RMuint32 soft_irq_task_addr;
	/** Member default */
	enum TransferTaskDirection direction;
	/** Member default */
	enum TransferTaskFifoMode fifo_mode;
	/** Member default */
	RMuint32 size;
};

/** struct Default */
struct CPUBlock_AddRawDataXferTask_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 priority;
	/** Member default */
	RMuint32 host_notification_threshold;
	/** Member default */
	enum TransferTaskCallback callback;
	/** Member default */
	void * context;
	/** Member default */
	RMuint32 soft_irq_task_addr;
	/** Member default */
	enum TransferTaskDirection direction;
	/** Member default */
	RMuint32 size;
};

/** struct Default */
struct CPUBlock_AddSoftIrqTask_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 task_head;
	/** Member default */
	RMuint32 module_id;
	/** Member default */
	RMuint32 mutex;
	/** Member default */
	RMuint32 pMask;
	/** Member default */
	RMuint32 pStatus;
	/** Member default */
	RMuint32 status_fifo_addr;
};

/** struct Default */
struct CPUBlock_DataFifoChunk_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 src;
	/** Member default */
	RMuint32 size;
	/** Member default */
	void * context;
	/** Member default */
	RMuint32 pts;
	/** Member default */
	RMbool pts_valid;
	/** Member default */
	RMuint32 first_access_unit_pointer;
};

/** struct Default */
struct CPUBlock_RawDataChunk_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 src;
	/** Member default */
	RMuint32 size;
	/** Member default */
	void * context;
};

/** struct Default */
struct CPUBlock_AddDataFifoReadBuffer_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 src;
	/** Member default */
	RMuint32 size;
	/** Member default */
	void * context;
};

/** struct Default */
struct CPUBlock_AddRawDataReadBuffer_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 src;
	/** Member default */
	RMuint32 size;
	/** Member default */
	void * context;
};

/** struct Default */
struct CPUBlock_ProgramRawDataXfer_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 Address;
	/** Member default */
	RMuint32 Size;
	/** Member default */
	RMuint32 Width;
	/** Member default */
	RMuint32 TotalWidth;
	/** Member default */
	RMbool Tiled;
};

/** struct Default */
struct CPUBlock_Error_type {
	/** Member default */
	RMuint32 module_id;
	/** Member default */
	RMstatus error;
	/** Member default */
	RMuint32 time;
};

/** struct Default */
struct CPUBlock_EMhwlibError_type {
	/** Member default */
	RMuint32 module_id;
	/** Member default */
	RMstatus error;
	/** Member default */
	RMuint32 time;
};

/** struct Default */
struct CPUBlock_ReadBufferThreshold_type {
	/** Member default */
	RMuint32 task_address;
	/** Member default */
	RMuint32 threshold;
};

/** struct Default */
struct XPUBlock_Error_type {
	/** Member default */
	RMuint32 module_id;
	/** Member default */
	RMstatus error;
	/** Member default */
	RMuint32 time;
};

/** struct Default */
struct IPUBlock_Error_type {
	/** Member default */
	RMuint32 module_id;
	/** Member default */
	RMstatus error;
	/** Member default */
	RMuint32 time;
};

/** struct Default */
struct DisplayBlock_VsyncApiInfo_type {
	/** Member default */
	RMuint32 Address;
	/** Member default */
	RMuint32 Size;
};

/** initialize a picture fifo surface */
struct DisplayBlock_InitMultiplePictureSurface_type {
	/** format mode of the image */
	enum EMhwlibColorMode ColorMode;
	/** format submode of the image */
	enum EMhwlibColorFormat ColorFormat;
	/** Chroma mode of the image */
	enum EMhwlibSamplingMode SamplingMode;
	/** amount of data that has to be allocated by the application */
	RMuint32 Address;
	/** color space of the surface */
	enum EMhwlibColorSpace ColorSpace;
	/** pixel aspect ratio of the surface */
	struct EMhwlibAspectRatio PixelAspectRatio;
	/** number of pictures in the FIFO */
	RMuint32 PictureCount;
	/** index of the STC module */
	RMuint32 STCModuleId;
};

/** initialize a picture fifo surface */
struct DisplayBlock_InitMultiplePictureSurfaceX_type {
	/** format mode of the image */
	enum EMhwlibColorMode ColorMode;
	/** format submode of the image */
	enum EMhwlibColorFormat ColorFormat;
	/** Chroma mode of the image */
	enum EMhwlibSamplingMode SamplingMode;
	/** amount of data that has to be allocated by the application */
	RMuint32 Address;
	/** color space of the surface */
	enum EMhwlibColorSpace ColorSpace;
	/** pixel aspect ratio of the surface */
	struct EMhwlibAspectRatio PixelAspectRatio;
	/** number of pictures in the FIFO */
	RMuint32 PictureCount;
	/** index of the STC module */
	RMuint32 STCModuleId;
	/** TRUE is tiled pictures, FALSE is linear pictures */
	RMbool Tiled;
};

/** insert a picture inside the surface picture's fifo */
struct DisplayBlock_InsertPictureInSurfaceFifo_type {
	/** surface to insert the picture to */
	RMuint32 Surface;
	/** picture to insert in the surface's Fifo */
	RMuint32 Picture;
	/** pts of the inserted picture */
	RMuint64 Pts;
};

/** insert a picture inside the surface picture's fifo */
struct DisplayBlock_SetPaletteOnPicture_type {
	/** picture to insert in the surface's Fifo */
	RMuint32 Picture;
	/** picture to insert in the surface's Fifo */
	RMpalette_8BPP Palette;
	/** picture to insert in the surface's Fifo */
	RMuint32 PaletteSize;
};

/** initialize a static surface */
struct DisplayBlock_SurfaceAspectRatio_type {