clockmy.vhd

来自「ALTERA的语音芯片程序」· VHDL 代码 · 共 31 行

ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clockmy is
port(clk,over,reset:in std_logic;
	 sclk,start,mclk:out std_logic;
	 data:out std_logic_vector(23 downto 0));
end clockmy;
architecture bhv of clockmy is
signal sclktemp,mclktemp:std_logic;
signal cnt1:integer 0 to 2;
signal cnt2:integer 0 to 23;
signal vol :std_logic_vector(6 downto 0); 
begin
process(clk)
begin
 if clk'event and clk='1'
  if cnt2=23 then cnt2<=0;sclk<=not sclk;
  else cnt2<=cnt2+1;
  end if;
  if cnt1=1 then cnt1<=0;mclk<=not mclk;
  else cnt1<=cnt1+1;
  end if;
 end if;
end process;
process(reset)
begin
 if reset'event and reset='1' then
  if vol="0111101" and