audio.tan.qmsg

来自「ALTERA的语音芯片程序」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 5 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sdo register sdo 349.28 MHz 2.863 ns Internal " "Info: Clock \"clk\" has Internal fmax of 349.28 MHz between source register \"sdo\" and destination register \"sdo\" (period= 2.863 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.649 ns + Longest register register " "Info: + Longest register to register delay is 2.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sdo 1 REG LCFF_X47_Y27_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sdo } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.438 ns) 0.924 ns Mux1~549 2 COMB LCCOMB_X48_Y27_N4 1 " "Info: 2: + IC(0.486 ns) + CELL(0.438 ns) = 0.924 ns; Loc. = LCCOMB_X48_Y27_N4; Fanout = 1; COMB Node = 'Mux1~549'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.924 ns" { sdo Mux1~549 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.150 ns) 1.513 ns Mux1~550 3 COMB LCCOMB_X47_Y27_N16 1 " "Info: 3: + IC(0.439 ns) + CELL(0.150 ns) = 1.513 ns; Loc. = LCCOMB_X47_Y27_N16; Fanout = 1; COMB Node = 'Mux1~550'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.589 ns" { Mux1~549 Mux1~550 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.271 ns) 2.038 ns Mux1~551 4 COMB LCCOMB_X47_Y27_N20 1 " "Info: 4: + IC(0.254 ns) + CELL(0.271 ns) = 2.038 ns; Loc. = LCCOMB_X47_Y27_N20; Fanout = 1; COMB Node = 'Mux1~551'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.525 ns" { Mux1~550 Mux1~551 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.256 ns) + CELL(0.271 ns) 2.565 ns Mux1~561 5 COMB LCCOMB_X47_Y27_N30 1 " "Info: 5: + IC(0.256 ns) + CELL(0.271 ns) = 2.565 ns; Loc. = LCCOMB_X47_Y27_N30; Fanout = 1; COMB Node = 'Mux1~561'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.527 ns" { Mux1~551 Mux1~561 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.649 ns sdo 6 REG LCFF_X47_Y27_N31 3 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.649 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux1~561 sdo } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.214 ns ( 45.83 % ) " "Info: Total cell delay = 1.214 ns ( 45.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.435 ns ( 54.17 % ) " "Info: Total interconnect delay = 1.435 ns ( 54.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { sdo Mux1~549 Mux1~550 Mux1~551 Mux1~561 sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { sdo Mux1~549 Mux1~550 Mux1~551 Mux1~561 sdo } { 0.000ns 0.486ns 0.439ns 0.254ns 0.256ns 0.000ns } { 0.000ns 0.438ns 0.150ns 0.271ns 0.271ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.643 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 27 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.537 ns) 2.643 ns sdo 3 REG LCFF_X47_Y27_N31 3 " "Info: 3: + IC(0.989 ns) + CELL(0.537 ns) = 2.643 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl sdo } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.12 % ) " "Info: Total cell delay = 1.536 ns ( 58.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.107 ns ( 41.88 % ) " "Info: Total interconnect delay = 1.107 ns ( 41.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.643 ns" { clk clk~clkctrl sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.643 ns" { clk clk~combout clk~clkctrl sdo } { 0.000ns 0.000ns 0.118ns 0.989ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.643 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 27 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.537 ns) 2.643 ns sdo 3 REG LCFF_X47_Y27_N31 3 " "Info: 3: + IC(0.989 ns) + CELL(0.537 ns) = 2.643 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl sdo } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.12 % ) " "Info: Total cell delay = 1.536 ns ( 58.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.107 ns ( 41.88 % ) " "Info: Total interconnect delay = 1.107 ns ( 41.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.643 ns" { clk clk~clkctrl sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.643 ns" { clk clk~combout clk~clkctrl sdo } { 0.000ns 0.000ns 0.118ns 0.989ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.643 ns" { clk clk~clkctrl sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.643 ns" { clk clk~combout clk~clkctrl sdo } { 0.000ns 0.000ns 0.118ns 0.989ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.643 ns" { clk clk~clkctrl sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.643 ns" { clk clk~combout clk~clkctrl sdo } { 0.000ns 0.000ns 0.118ns 0.989ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { sdo Mux1~549 Mux1~550 Mux1~551 Mux1~561 sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { sdo Mux1~549 Mux1~550 Mux1~551 Mux1~561 sdo } { 0.000ns 0.486ns 0.439ns 0.254ns 0.256ns 0.000ns } { 0.000ns 0.438ns 0.150ns 0.271ns 0.271ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.643 ns" { clk clk~clkctrl sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.643 ns" { clk clk~combout clk~clkctrl sdo } { 0.000ns 0.000ns 0.118ns 0.989ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.643 ns" { clk clk~clkctrl sdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.643 ns" { clk clk~combout clk~clkctrl sdo } { 0.000ns 0.000ns 0.118ns 0.989ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}