audio.fit.qmsg

来自「ALTERA的语音芯片程序」· QMSG 代码 · 共 34 行 · 第 1/3 页

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.048 ns register register " "Info: Estimated most critical path is register to register delay of 3.048 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sd\[10\] 1 REG LAB_X48_Y27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X48_Y27; Fanout = 1; REG Node = 'sd\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sd[10] } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.644 ns) + CELL(0.438 ns) 1.082 ns Mux1~556 2 COMB LAB_X46_Y27 1 " "Info: 2: + IC(0.644 ns) + CELL(0.438 ns) = 1.082 ns; Loc. = LAB_X46_Y27; Fanout = 1; COMB Node = 'Mux1~556'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.082 ns" { sd[10] Mux1~556 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.150 ns) 1.838 ns Mux1~557 3 COMB LAB_X47_Y27 1 " "Info: 3: + IC(0.606 ns) + CELL(0.150 ns) = 1.838 ns; Loc. = LAB_X47_Y27; Fanout = 1; COMB Node = 'Mux1~557'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.756 ns" { Mux1~556 Mux1~557 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.271 ns) 2.399 ns Mux1~560 4 COMB LAB_X47_Y27 1 " "Info: 4: + IC(0.290 ns) + CELL(0.271 ns) = 2.399 ns; Loc. = LAB_X47_Y27; Fanout = 1; COMB Node = 'Mux1~560'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.561 ns" { Mux1~557 Mux1~560 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 2.964 ns Mux1~561 5 COMB LAB_X47_Y27 1 " "Info: 5: + IC(0.145 ns) + CELL(0.420 ns) = 2.964 ns; Loc. = LAB_X47_Y27; Fanout = 1; COMB Node = 'Mux1~561'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { Mux1~560 Mux1~561 } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.048 ns sdo 6 REG LAB_X47_Y27 3 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.048 ns; Loc. = LAB_X47_Y27; Fanout = 3; REG Node = 'sdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux1~561 sdo } "NODE_NAME" } } { "audio1.vhd" "" { Text "G:/debug/audio/audio1.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.363 ns ( 44.72 % ) " "Info: Total cell delay = 1.363 ns ( 44.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.685 ns ( 55.28 % ) " "Info: Total interconnect delay = 1.685 ns ( 55.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.048 ns" { sd[10] Mux1~556 Mux1~557 Mux1~560 Mux1~561 sdo } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "3 " "Warning: Found 3 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i2s_data 0 " "Info: Pin \"i2s_data\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i2s_sclk 0 " "Info: Pin \"i2s_sclk\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "over 0 " "Info: Pin \"over\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 16 22:15:38 2008 " "Info: Processing ended: Tue Dec 16 22:15:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/debug/audio/audio.fit.smsg " "Info: Generated suppressed messages file G:/debug/audio/audio.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}