mux_klc.tdf

ALTERA的语音芯片程序

--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Cyclone II" IGNORE_CASCADE_BUFFERS="ON" LPM_SIZE=32 LPM_WIDTH=1 LPM_WIDTHS=5 data result sel
--VERSION_BEGIN 6.0 cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 21 
SUBDESIGN mux_klc
( 
	data[31..0]	:	input;
	result[0..0]	:	output;
	sel[4..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[9..0]	: WIRE;
	sel_node[4..0]	: WIRE;
	w_data113w[15..0]	: WIRE;
	w_data114w[15..0]	: WIRE;
	w_data124w[3..0]	: WIRE;
	w_data125w[3..0]	: WIRE;
	w_data126w[3..0]	: WIRE;
	w_data127w[3..0]	: WIRE;
	w_data12w[31..0]	: WIRE;
	w_data227w[3..0]	: WIRE;
	w_data228w[3..0]	: WIRE;
	w_data229w[3..0]	: WIRE;
	w_data230w[3..0]	: WIRE;
	w_result111w	: WIRE;
	w_result112w	: WIRE;
	w_result120w	: WIRE;
	w_result121w	: WIRE;
	w_result122w	: WIRE;
	w_result123w	: WIRE;
	w_result135w	: WIRE;
	w_result156w	: WIRE;
	w_result173w	: WIRE;
	w_result190w	: WIRE;
	w_result206w	: WIRE;
	w_result223w	: WIRE;
	w_result224w	: WIRE;
	w_result225w	: WIRE;
	w_result226w	: WIRE;
	w_result237w	: WIRE;
	w_result258w	: WIRE;
	w_result275w	: WIRE;
	w_result292w	: WIRE;
	w_result308w	: WIRE;
	w_sel115w[3..0]	: WIRE;
	w_sel128w[1..0]	: WIRE;
	w_sel231w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( ((sel_node[4..4] & w_result112w) # ((! sel_node[4..4]) & w_result111w)));
	sel_ffs_wire[] = ( sel_ffs_wire[4..0], sel[4..0]);
	sel_node[] = ( sel_ffs_wire[9..9], sel_ffs_wire[3..2], sel[1..0]);
	w_data113w[15..0] = w_data12w[15..0];
	w_data114w[15..0] = w_data12w[31..16];
	w_data124w[3..0] = w_data113w[3..0];
	w_data125w[3..0] = w_data113w[7..4];
	w_data126w[3..0] = w_data113w[11..8];
	w_data127w[3..0] = w_data113w[15..12];
	w_data12w[] = ( data[31..0]);
	w_data227w[3..0] = w_data114w[3..0];
	w_data228w[3..0] = w_data114w[7..4];
	w_data229w[3..0] = w_data114w[11..8];
	w_data230w[3..0] = w_data114w[15..12];
	w_result111w = (((w_result121w & w_sel115w[2..2]) & (! w_result206w)) # (w_result206w & (w_result123w # (! w_sel115w[2..2]))));
	w_result112w = (((w_result224w & w_sel115w[2..2]) & (! w_result308w)) # (w_result308w & (w_result226w # (! w_sel115w[2..2]))));
	w_result120w = (((w_data124w[1..1] & w_sel128w[0..0]) & (! w_result135w)) # (w_result135w & (w_data124w[3..3] # (! w_sel128w[0..0]))));
	w_result121w = (((w_data125w[1..1] & w_sel128w[0..0]) & (! w_result156w)) # (w_result156w & (w_data125w[3..3] # (! w_sel128w[0..0]))));
	w_result122w = (((w_data126w[1..1] & w_sel128w[0..0]) & (! w_result173w)) # (w_result173w & (w_data126w[3..3] # (! w_sel128w[0..0]))));
	w_result123w = (((w_data127w[1..1] & w_sel128w[0..0]) & (! w_result190w)) # (w_result190w & (w_data127w[3..3] # (! w_sel128w[0..0]))));
	w_result135w = (((w_data124w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data124w[2..2])));
	w_result156w = (((w_data125w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data125w[2..2])));
	w_result173w = (((w_data126w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data126w[2..2])));
	w_result190w = (((w_data127w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data127w[2..2])));
	w_result206w = (((w_result120w & (! w_sel115w[3..3])) & (! w_sel115w[2..2])) # (w_sel115w[3..3] & (w_sel115w[2..2] # w_result122w)));
	w_result223w = (((w_data227w[1..1] & w_sel231w[0..0]) & (! w_result237w)) # (w_result237w & (w_data227w[3..3] # (! w_sel231w[0..0]))));
	w_result224w = (((w_data228w[1..1] & w_sel231w[0..0]) & (! w_result258w)) # (w_result258w & (w_data228w[3..3] # (! w_sel231w[0..0]))));
	w_result225w = (((w_data229w[1..1] & w_sel231w[0..0]) & (! w_result275w)) # (w_result275w & (w_data229w[3..3] # (! w_sel231w[0..0]))));
	w_result226w = (((w_data230w[1..1] & w_sel231w[0..0]) & (! w_result292w)) # (w_result292w & (w_data230w[3..3] # (! w_sel231w[0..0]))));
	w_result237w = (((w_data227w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data227w[2..2])));
	w_result258w = (((w_data228w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data228w[2..2])));
	w_result275w = (((w_data229w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data229w[2..2])));
	w_result292w = (((w_data230w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data230w[2..2])));
	w_result308w = (((w_result223w & (! w_sel115w[3..3])) & (! w_sel115w[2..2])) # (w_sel115w[3..3] & (w_sel115w[2..2] # w_result225w)));
	w_sel115w[3..0] = sel_node[3..0];
	w_sel128w[1..0] = w_sel115w[1..0];
	w_sel231w[1..0] = w_sel115w[1..0];
END;
--VALID FILE