changer.vhd

ALTERA的语音芯片程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity changer is
port(clk,start,din,down,test : in std_logic;
     dout : out std_logic_vector(15 downto 0);
     full : out std_logic;
     testout : out std_logic_vector(15 downto 0));
end;
architecture bhv of changer is
type memory is array(0 to 15) of std_logic_vector(15 downto 0);
signal temp : std_logic_vector(15 downto 0);
signal a,atemp,x : integer range 0 to 15;
signal fulltemp : std_logic;
signal flag : std_logic:='0';

begin
 full<=fulltemp;
 process(start)
 begin
  if start'event and start='1' then flag<='1'; end if;
 end process;
 process(clk,flag)
 begin
  if clk'event and clk='1' then 
   if flag='0' then temp<=(others=>'0');a<=0;x<=15;
   else temp(x)<=din;if x=0 then x<=15;fulltemp<='1';else x<=x-1;fulltemp<='0';end if;
   end if;
   if fulltemp='1' then 
    if a=15 then a<=0;else a<=a+1;end if;
   end if;
  end if;
 end process;
 process(down)
 begin
  if down'event and down='0' then
   if atemp=15 then atemp<=0;
   else atemp<=atemp+1;
   end if;
  end if;
 end process;
 process(clk,test,fulltemp,down,a,atemp)
 variable data : memory;
 begin
  if clk'event and clk='0' then
   if fulltemp='1' then data(a):=temp;end if;
   if down='1' then dout<=data(atemp);end if;
   if test='1' and down='1' then testout<=data(atemp);end if;
  end if;
 end process;
end;